1 /* SPDX-License-Identifier: GPL-2.0+ */
3  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
8  *	Contains standard defines and IDs for NAND flash devices
35 /* Scan and identify a NAND device */
39  * and override command or ECC setup according to flash type.
45 /* Free resources held by the NAND device */
77  * Standard NAND flash commands
104 /* Extended commands for AG-AND device */
115 /* multi-bank error status (banks 0-3) */
123 #define NAND_CMD_NONE		-1
132 #define NAND_DATA_IFACE_CHECK_ONLY	-1
153  * Constants for Hardware ECC
155 /* Reset Hardware ECC for read */
157 /* Reset Hardware ECC for write */
159 /* Enable Hardware ECC before syndrome is read back from flash */
163  * Enable generic NAND 'page erased' check. This check is only done when
164  * ecc.correct() returns -EBADMSG.
171  * If your controller already sends the required NAND commands when
194  * Chip requires ready check on read (for auto-incremented sequential read).
203 /* Device is one of 'new' xD cards that expose fake nand command set */
206 /* Device behaves just like nand, but is readonly */
225 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
226 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
227 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
234  * (e.g. because it needs them DMA-coherent).
240  * Autodetect nand buswidth with readid/onfi.
252 /* Options set by nand scan */
255 /* Nand scan has allocated controller struct */
279 /* Vendor-specific feature address (Micron) */
356 /* Extended ECC information Block Definition (since ONFI 2.1) */
367 #define ONFI_SECTION_TYPE_2	2	/* for ECC information. */
471 	/* ECC and endurance block */
489 …* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared am…
492  * @wq:			wait queue to sleep on if a NAND operation is in
502  * struct nand_ecc_step_info - ECC step information of ECC engine
503  * @stepsize: data bytes per ECC step
514  * struct nand_ecc_caps - capability of ECC engine
515  * @stepinfos: array of ECC step information
516  * @nstepinfos: number of ECC step information
517  * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
525 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
540  * struct nand_ecc_ctrl - Control structure for ECC
541  * @mode:	ECC mode
542  * @algo:	ECC algorithm
543  * @steps:	number of ECC steps per page
544  * @size:	data bytes per ECC step
545  * @bytes:	ECC bytes per step
546  * @strength:	max number of correctible bits per ECC step
547  * @total:	total number of ECC bytes per page
548  * @prepad:	padding information for syndrome based ECC generators
549  * @postpad:	padding information for syndrome based ECC generators
550  * @options:	ECC specific options (see NAND_ECC_XXX flags defined above)
551  * @layout:	ECC layout control struct pointer
552  * @priv:	pointer to private ECC control data
553  * @hwctl:	function to control hardware ECC generator. Must only
554  *		be provided if an hardware ECC is available
555  * @calculate:	function for ECC calculation or readback from ECC hardware
556  * @correct:	function for ECC correction, matching to ECC generator (sw/hw).
558  *		corrected bitflips, -EBADMSG if the number of bitflips exceed
559  *		ECC strength, or any other error code if the error is not
561  *		If -EBADMSG is returned the input buffers should be left
563  * @read_page_raw:	function to read a raw page without ECC. This function
564  *			should hide the specific layout used by the ECC
565  *			controller and always return contiguous in-band and
566  *			out-of-band data even if they're not stored
567  *			contiguously on the NAND chip (e.g.
568  *			NAND_ECC_HW_SYNDROME interleaves in-band and
569  *			out-of-band data).
570  * @write_page_raw:	function to write a raw page without ECC. This function
571  *			should hide the specific layout used by the ECC
573  *			in-band and out-of-band data. ECC controller is
576  *			NAND_ECC_HW_SYNDROME interleaves in-band and
577  *			out-of-band data).
578  * @read_page:	function to read a page according to the ECC generator
580  *		any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
581  * @read_subpage:	function to read parts of the page covered by ECC;
583  * @write_subpage:	function to write parts of the page covered by ECC.
584  * @write_page:	function to write a page according to the ECC generator
586  * @write_oob_raw:	function to write chip OOB data without ECC
587  * @read_oob_raw:	function to read chip OOB data without ECC
593 	enum nand_ecc_algo algo;  member
631 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)  in nand_standard_page_accessors()  argument
633 	return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);  in nand_standard_page_accessors()
637  * struct nand_buffers - buffer structure for read/write
638  * @ecccalc:	buffer pointer for calculated ECC, size is oobsize.
639  * @ecccode:	buffer pointer for ECC read from flash, size is oobsize.
653  * struct nand_sdr_timings - SDR NAND chip timings
655  * This struct defines the timing requirements of a SDR NAND chip.
656  * These information can be found in every NAND datasheets and the timings
674  * @tCHZ_max: CE# high to output hi-Z
683  * @tIR_min: Output hi-Z to RE# low
690  * @tRHZ_max: RE# high to output hi-Z
745  * enum nand_data_interface_type - NAND interface timing type
753  * struct nand_data_interface - NAND interface timing
765  * nand_get_sdr_timings - get SDR timing from data interface
771 	if (conf->type != NAND_SDR_IFACE)  in nand_get_sdr_timings()
772 		return ERR_PTR(-EINVAL);  in nand_get_sdr_timings()
774 	return &conf->timings.sdr;  in nand_get_sdr_timings()
778  * struct nand_chip - NAND Private Flash Chip Data
805  *			setting the read-retry mode. Mostly needed for MLC NAND.
806  * @ecc:		[BOARDSPECIFIC] ECC control structure
809  * @hwcontrol:		platform-specific hardware control structure
814  * @state:		[INTERN] the current state of the NAND device
834  * @ecc_strength_ds:	[INTERN] ECC correctability from the datasheet.
837  * @ecc_step_ds:	[INTERN] ECC step required by the @ecc_strength_ds,
838  *                      also from the datasheet. It is the recommended ECC step
843  *			      the NAND chip is not ONFI compliant.
846  * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
861  * @onfi_set_features:	[REPLACEABLE] set the features for ONFI nand
862  * @onfi_get_features:	[REPLACEABLE] get the features for ONFI nand
877  * @write_page:		[REPLACEABLE] High-level page write function
950 	struct nand_ecc_ctrl ecc;  member
971 	return &chip->mtd;  in nand_to_mtd()
976 	return chip->priv;  in nand_get_controller_data()
981 	chip->priv = priv;  in nand_set_controller_data()
985  * NAND Flash Manufacturer ID Codes
1002 /* The maximum expected count of bytes in the NAND ID sequence */
1006  * A helper for defining older NAND chips where the second ID byte fully
1008  * size). All these chips have 512 bytes NAND page size.
1030 #define NAND_ECC_STRENGTH(type)		((type)->ecc.strength_ds)
1031 #define NAND_ECC_STEP(type)		((type)->ecc.step_ds)
1034  * struct nand_flash_dev - NAND Flash Device ID Structure
1035  * @name: a human-readable name of the NAND chip
1042  * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1043  *            well as the eraseblock size) is determined from the extended NAND
1050  * @ecc: ECC correctability and step information from the datasheet.
1051  * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1053  * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1055  *               For example, the "4bit ECC for each 512Byte" can be set with
1057  * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1080 	} ecc;  member
1085  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
1113  * struct platform_nand_chip - chip level device structure
1121  * @part_probe_types:	NULL-terminated array of probe types
1138  * struct platform_nand_ctrl - controller level device structure
1167  * struct platform_nand_data - container structure for platform-specific data
1180 	return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;  in onfi_feature()
1186 	if (!chip->onfi_version)  in onfi_get_async_timing_mode()
1188 	return le16_to_cpu(chip->onfi_params.async_timing_mode);  in onfi_get_async_timing_mode()
1194 	if (!chip->onfi_version)  in onfi_get_sync_timing_mode()
1196 	return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);  in onfi_get_sync_timing_mode()
1221  * Check if it is a SLC nand.
1222  * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1227 	return chip->bits_per_cell == 1;  in nand_is_slc()
1251 	return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)  in jedec_feature()
1255 /* Standard NAND functions from nand_base.c */
1268 				void *ecc, int ecclen,
1281 /* Reset and initialize a NAND device */