linux/mtd/rawnand.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
65 /* Select the chip by setting nCE to low */
67 /* Select the command latch by setting CLE to high */
69 /* Select the address latch by setting ALE to high */
104 /* Extended commands for AG-AND device */
115 /* multi-bank error status (banks 0-3) */
123 #define NAND_CMD_NONE		-1
132 #define NAND_DATA_IFACE_CHECK_ONLY	-1
164  * ecc.correct() returns -EBADMSG.
194  * Chip requires ready check on read (for auto-incremented sequential read).
225 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
226 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
227 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
234  * (e.g. because it needs them DMA-coherent).
279 /* Vendor-specific feature address (Micron) */
489 …* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared am…
502  * struct nand_ecc_step_info - ECC step information of ECC engine
514  * struct nand_ecc_caps - capability of ECC engine
540  * struct nand_ecc_ctrl - Control structure for ECC
558  *		corrected bitflips, -EBADMSG if the number of bitflips exceed
561  *		If -EBADMSG is returned the input buffers should be left
565  *			controller and always return contiguous in-band and
566  *			out-of-band data even if they're not stored
568  *			NAND_ECC_HW_SYNDROME interleaves in-band and
569  *			out-of-band data).
573  *			in-band and out-of-band data. ECC controller is
576  *			NAND_ECC_HW_SYNDROME interleaves in-band and
577  *			out-of-band data).
580  *		any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
605 	int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
607 	int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
633 	return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);  in nand_standard_page_accessors()
637  * struct nand_buffers - buffer structure for read/write
653  * struct nand_sdr_timings - SDR NAND chip timings
670  * @tAR_min: ALE to RE# delay
674  * @tCHZ_max: CE# high to output hi-Z
676  * @tCLR_min: CLE to RE# delay
683  * @tIR_min: Output hi-Z to RE# low
690  * @tRHZ_max: RE# high to output hi-Z
745  * enum nand_data_interface_type - NAND interface timing type
753  * struct nand_data_interface - NAND interface timing
765  * nand_get_sdr_timings - get SDR timing from data interface
771 	if (conf->type != NAND_SDR_IFACE)  in nand_get_sdr_timings()
772 		return ERR_PTR(-EINVAL);  in nand_get_sdr_timings()
774 	return &conf->timings.sdr;  in nand_get_sdr_timings()
778  * struct nand_chip - NAND Private Flash Chip Data
791  * @select_chip:	[REPLACEABLE] select chip nr
805  *			setting the read-retry mode. Mostly needed for MLC NAND.
809  * @hwcontrol:		platform-specific hardware control structure
812  * @chip_delay:		[BOARDSPECIFIC] chip dependent delay for transferring
846  * @pagemask:		[INTERN] page number mask = number of (pages / chip) - 1
877  * @write_page:		[REPLACEABLE] High-level page write function
895 	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
971 	return &chip->mtd;  in nand_to_mtd()
976 	return chip->priv;  in nand_get_controller_data()
981 	chip->priv = priv;  in nand_set_controller_data()
1030 #define NAND_ECC_STRENGTH(type)		((type)->ecc.strength_ds)
1031 #define NAND_ECC_STEP(type)		((type)->ecc.step_ds)
1034  * struct nand_flash_dev - NAND Flash Device ID Structure
1035  * @name: a human-readable name of the NAND chip
1085  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
1113  * struct platform_nand_chip - chip level device structure
1118  * @chip_delay:		R/B delay value in us
1121  * @part_probe_types:	NULL-terminated array of probe types
1138  * struct platform_nand_ctrl - controller level device structure
1143  * @select_chip:	platform specific chip select function
1156 	void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1159 	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1167  * struct platform_nand_data - container structure for platform-specific data
1180 	return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;  in onfi_feature()
1186 	if (!chip->onfi_version)  in onfi_get_async_timing_mode()
1188 	return le16_to_cpu(chip->onfi_params.async_timing_mode);  in onfi_get_async_timing_mode()
1194 	if (!chip->onfi_version)  in onfi_get_sync_timing_mode()
1196 	return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);  in onfi_get_sync_timing_mode()
1227 	return chip->bits_per_cell == 1;  in nand_is_slc()
1251 	return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)  in jedec_feature()