Lines Matching +full:0 +full:x01400000

16 #define QE_MURAM_SIZE		0xc000UL
20 #define QE_MURAM_SIZE 0x4000UL
27 #define QE_MURAM_SIZE 0x6000UL
33 #define QE_IMMR_OFFSET 0x00140000
35 #define QE_IMMR_OFFSET 0x01400000
42 u8 res0[0x4];
44 u8 res1[0x70];
60 u8 res0[0x4];
63 u8 res1[0x4];
65 u8 res2[0x20];
67 u8 res3[0x1C];
75 u8 res0[0xA];
77 u8 res1[0x2];
82 u8 res2[0x8];
86 u8 res3[0x2];
87 u8 res4[0x24];
89 u8 res5[0x2];
91 u8 res6[0x2];
93 u8 res7[0x2];
95 u8 res8[0x2];
97 u8 res9[0x2];
99 u8 res10[0x2];
101 u8 res11[0x2];
103 u8 res12[0x2];
104 u8 res13[0x280];
118 u8 res0[0x1C];
124 u8 res0[0x3];
126 u8 res1[0xB];
148 u8 res2[0x46];
169 u8 res0[0x40];
174 u8 res0[0x20];
176 u8 res1[0x2];
178 u8 res2[0x1];
179 u8 res3[0x2];
181 u8 res4[0x1];
182 u8 res5[0x1];
184 u8 res6[0x2];
187 u8 res7[0x8];
197 u8 res0[0x1];
199 u8 res2[0x1];
201 u8 res3[0x1];
211 u8 res4[0x8];
217 u8 res5[0x1];
219 u8 res6[0x1];
221 u8 res7[0x1];
231 u8 res8[0x8];
234 u8 res9[0xBB];
239 u8 tx[0x400];
240 u8 rx[0x400];
241 u8 res0[0x800];
263 u8 res6[0x22];
272 u8 res0[0xF0];
280 u8 res0[0x2];
284 u8 res1[0x2];
286 u8 res2[0x1];
288 u8 res3[0x24];
291 u8 res4[0x200 - 0x091];
310 u8 res1[0x10];
321 u8 res2[0x8];
325 u8 res3[0x180 - 0x15A];
355 u8 res4[0x2];
376 u8 res5[0x200 - 0x1c4];
384 u8 res0[0x2];
386 u8 res1[0x2];
390 u8 res2[0x7];
393 u8 res3[0x2];
399 u8 res4[0x2];
401 u8 res5[0x2];
403 u8 res6[0x2];
405 u8 res7[0x2];
407 u8 res8[0x4C];
409 u8 res9[0x100 - 0x091];
415 u8 res1[0x90];
417 u8 res2[0x200 - 0x091];
439 u8 res0[0xC];
460 u8 res1[0x8];
461 u16 uptirr1_0; /* Device 1 transmit internal rate 0 */
465 u16 uptirr2_0; /* Device 2 transmit internal rate 0 */
469 u16 uptirr3_0; /* Device 3 transmit internal rate 0 */
473 u16 uptirr4_0; /* Device 4 transmit internal rate 0 */
481 u8 res2[0x150];
496 u8 res0[0x10];
499 u8 res1[0x4];
501 u8 res2[0x38];
509 u32 bprmrr0; /* Breakpoint request mode risc register 0 */
511 u8 res0[0x8];
512 u32 bprmtr0; /* Breakpoint request mode trb register 0 */
514 u8 res1[0x8];
518 u8 res2[0x48];
553 u8 res4[0x100-0xf8];
562 spi_t spi[0x2]; /* spi */
567 u8 res11[0x800];
573 u8 res12[0x600];
579 u8 res13[0x600];
583 rsp_t rsp[0x2]; /* RISC Special Registers
585 u8 res14[0x300];
586 u8 res15[0x3A00];
587 u8 res16[0x8000]; /* 0x108000 - 0x110000 */