Lines Matching full:rx
35 u32 rx_frame_u; /* Rx frame counter upper */
36 u32 rx_frame_l; /* Rx frame counter lower */
37 u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */
38 u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */
39 u32 rx_align_err_u; /* Rx alignment error upper */
40 u32 rx_align_err_l; /* Rx alignment error lower */
43 u32 rx_pause_frame_u; /* Rx valid pause frame upper */
44 u32 rx_pause_frame_l; /* Rx valid pause frame upper */
45 u32 rx_long_err_u; /* Rx too long frame error upper */
46 u32 rx_long_err_l; /* Rx too long frame error lower */
47 u32 rx_frame_err_u; /* Rx frame length error upper */
48 u32 rx_frame_err_l; /* Rx frame length error lower */
51 u32 rx_vlan_u; /* Rx VLAN frame upper */
52 u32 rx_vlan_l; /* Rx VLAN frame lower */
55 u32 rx_oct_u; /* Rx octets upper */
56 u32 rx_oct_l; /* Rx octets lower */
57 u32 rx_uni_u; /* Rx unicast frame upper */
58 u32 rx_uni_l; /* Rx unicast frame lower */
59 u32 rx_multi_u; /* Rx multicast frame upper */
60 u32 rx_multi_l; /* Rx multicast frame lower */
61 u32 rx_brd_u; /* Rx broadcast frame upper */
62 u32 rx_brd_l; /* Rx broadcast frame lower */
71 u32 rx_drop_u; /* Rx dropped packets upper */
72 u32 rx_drop_l; /* Rx dropped packets lower */
73 u32 rx_eoct_u; /* Rx ethernet octets upper */
74 u32 rx_eoct_l; /* Rx ethernet octets lower */
75 u32 rx_pkt_u; /* Rx packets upper */
76 u32 rx_pkt_l; /* Rx packets lower */
79 u32 rx_64_u; /* Rx 64 oct packet upper */
80 u32 rx_64_l; /* Rx 64 oct packet lower */
81 u32 rx_127_u; /* Rx 65 to 127 oct packet upper */
82 u32 rx_127_l; /* Rx 65 to 127 oct packet lower */
83 u32 rx_255_u; /* Rx 128 to 255 oct packet upper */
84 u32 rx_255_l; /* Rx 128 to 255 oct packet lower */
85 u32 rx_511_u; /* Rx 256 to 511 oct packet upper */
86 u32 rx_511_l; /* Rx 256 to 511 oct packet lower */
87 u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */
88 u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */
89 u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */
90 u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */
91 u32 rx_1519_u; /* Rx 1519 to max oct packet upper */
92 u32 rx_1519_l; /* Rx 1519 to max oct packet lower */
99 u32 rx_err_u; /* Rx frame error upper */
100 u32 rx_err_l; /* Rx frame error lower */
114 #define TGEC_CMD_CFG_RX_ER_DISC 0x00004000 /* Rx err frm discard enb */
115 #define TGEC_CMD_CFG_CMD_FRM_EN 0x00002000 /* CMD frame RX enable */
120 #define TGEC_CMD_CFG_CRC_FWD 0x00000040 /* fwd Rx CRC frames */
121 #define TGEC_CMD_CFG_PAD_EN 0x00000020 /* MAC remove Rx padding */
124 #define TGEC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */
129 #define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */
143 #define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */
144 #define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */
145 #define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */
146 #define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */
147 #define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */
148 #define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */
149 #define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */
150 #define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */
151 #define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */
163 #define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */
164 #define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */
165 #define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */
166 #define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */
167 #define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */
168 #define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */
169 #define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */
170 #define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */
171 #define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */