u-boot/include/fsl_tgec.h

19 	u32	maxfrm;		/* Maximum frame length register */
33 	u32	tx_frame_u;	/* Tx frame counter upper */
34 	u32	tx_frame_l;	/* Tx frame counter lower */
35 	u32	rx_frame_u;	/* Rx frame counter upper */
36 	u32	rx_frame_l;	/* Rx frame counter lower */
37 	u32	rx_frame_crc_err_u; /* Rx frame check sequence error upper */
38 	u32	rx_frame_crc_err_l; /* Rx frame check sequence error lower */
41 	u32	tx_pause_frame_u; /* Tx valid pause frame upper */
42 	u32	tx_pause_frame_l; /* Tx valid pause frame lower */
43 	u32	rx_pause_frame_u; /* Rx valid pause frame upper */
44 	u32	rx_pause_frame_l; /* Rx valid pause frame upper */
45 	u32	rx_long_err_u;	/* Rx too long frame error upper */
46 	u32	rx_long_err_l;	/* Rx too long frame error lower */
47 	u32	rx_frame_err_u;	/* Rx frame length error upper */
48 	u32	rx_frame_err_l;	/* Rx frame length error lower */
49 	u32	tx_vlan_u;	/* Tx VLAN frame upper */
50 	u32	tx_vlan_l;	/* Tx VLAN frame lower */
51 	u32	rx_vlan_u;	/* Rx VLAN frame upper */
52 	u32	rx_vlan_l;	/* Rx VLAN frame lower */
57 	u32	rx_uni_u;	/* Rx unicast frame upper */
58 	u32	rx_uni_l;	/* Rx unicast frame lower */
59 	u32	rx_multi_u;	/* Rx multicast frame upper */
60 	u32	rx_multi_l;	/* Rx multicast frame lower */
61 	u32	rx_brd_u;	/* Rx broadcast frame upper */
62 	u32	rx_brd_l;	/* Rx broadcast frame lower */
63 	u32	tx_frame_err_u;	/* Tx frame error upper */
64 	u32	tx_frame_err_l;	/* Tx frame error lower */
65 	u32	tx_uni_u;	/* Tx unicast frame upper */
66 	u32	tx_uni_l;	/* Tx unicast frame lower */
67 	u32	tx_multi_u;	/* Tx multicast frame upper */
68 	u32	tx_multi_l;	/* Tx multicast frame lower */
69 	u32	tx_brd_u;	/* Tx broadcast frame upper */
70 	u32	tx_brd_l;	/* Tx broadcast frame lower */
99 	u32	rx_err_u;	/* Rx frame error upper */
100 	u32	rx_err_l;	/* Rx frame error lower */
115 #define TGEC_CMD_CFG_CMD_FRM_EN		0x00002000 /* CMD frame RX enable */
140 #define IMASK_TX_ECC_ER		0x00001000 /* Tx frame ECC error mask */
142 #define IMASK_TX_ER		0x00000200 /* Tx frame error mask */
144 #define IMASK_RX_ECC_ER		0x00000080 /* Rx frame ECC error mask */
145 #define IMASK_RX_JAB_FRM	0x00000040 /* Rx jabber frame mask */
146 #define IMASK_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame mask */
147 #define IMASK_RX_RUNT_FRM	0x00000010 /* Rx runt frame mask */
148 #define IMASK_RX_FRAG_FRM	0x00000008 /* Rx fragment frame mask */
160 #define IEVENT_TX_ECC_ER	0x00001000 /* Tx frame ECC error */
162 #define IEVENT_TX_ER		0x00000200 /* Tx frame error */
164 #define IEVENT_RX_ECC_ER	0x00000080 /* Rx frame ECC error */
165 #define IEVENT_RX_JAB_FRM	0x00000040 /* Rx jabber frame */
166 #define IEVENT_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame */
167 #define IEVENT_RX_RUNT_FRM	0x00000010 /* Rx runt frame */
168 #define IEVENT_RX_FRAG_FRM	0x00000008 /* Rx fragment frame */