Lines Matching +full:inter +full:- +full:data

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright 2009-2011 Freescale Semiconductor, Inc.
17 	u32	mac_addr_0;	/* Lower 32 bits of 48-bit MAC address */
18 	u32	mac_addr_1;	/* Upper 16 bits of 48-bit MAC address */
25 	u32	tx_ipg_length;	/* Transmitter inter-packet-gap register */
26 	u32	mac_addr_2;	/* Lower 32 bits of the 2nd 48-bit MAC addr */
27 	u32	mac_addr_3;	/* Upper 16 bits of the 2nd 48-bit MAC addr */
104 /* EC10G_ID - 10-gigabit ethernet MAC controller ID */
109 /* COMMAND_CONFIG - command and configuration register */
128 /* HASHTABLE_CTRL - Hashtable control register */
132 /* TX_IPG_LENGTH - Transmit inter-packet gap length register */
135 /* IMASK - interrupt mask register */
155 /* IEVENT - interrupt event register */
179 	u32	mdio_data;	/* MDIO data */