u-boot/include/fsl_tgec.h

12 struct tgec {  struct
14 	u32	tgec_id;	/* Controller ID register */  argument
15 	u32	res0;
16 	u32	command_config;	/* Control and configuration register */
17 	u32	mac_addr_0;	/* Lower 32 bits of 48-bit MAC address */
18 	u32	mac_addr_1;	/* Upper 16 bits of 48-bit MAC address */
19 	u32	maxfrm;		/* Maximum frame length register */
20 	u32	pause_quant;	/* Pause quanta register */
21 	u32	res1[4];
22 	u32	hashtable_ctrl;	/* Hash table control register */
23 	u32	res2[4];
24 	u32	status;		/* MAC status register */
25 	u32	tx_ipg_length;	/* Transmitter inter-packet-gap register */
26 	u32	mac_addr_2;	/* Lower 32 bits of the 2nd 48-bit MAC addr */
27 	u32	mac_addr_3;	/* Upper 16 bits of the 2nd 48-bit MAC addr */
28 	u32	res3[4];
29 	u32	imask;		/* Interrupt mask register */
30 	u32	ievent;		/* Interrupt event register */
31 	u32	res4[6];
33 	u32	tx_frame_u;	/* Tx frame counter upper */
34 	u32	tx_frame_l;	/* Tx frame counter lower */
35 	u32	rx_frame_u;	/* Rx frame counter upper */
36 	u32	rx_frame_l;	/* Rx frame counter lower */
37 	u32	rx_frame_crc_err_u; /* Rx frame check sequence error upper */
38 	u32	rx_frame_crc_err_l; /* Rx frame check sequence error lower */
39 	u32	rx_align_err_u;	/* Rx alignment error upper */
40 	u32	rx_align_err_l;	/* Rx alignment error lower */
41 	u32	tx_pause_frame_u; /* Tx valid pause frame upper */
42 	u32	tx_pause_frame_l; /* Tx valid pause frame lower */
43 	u32	rx_pause_frame_u; /* Rx valid pause frame upper */
44 	u32	rx_pause_frame_l; /* Rx valid pause frame upper */
45 	u32	rx_long_err_u;	/* Rx too long frame error upper */
46 	u32	rx_long_err_l;	/* Rx too long frame error lower */
47 	u32	rx_frame_err_u;	/* Rx frame length error upper */
48 	u32	rx_frame_err_l;	/* Rx frame length error lower */
49 	u32	tx_vlan_u;	/* Tx VLAN frame upper */
50 	u32	tx_vlan_l;	/* Tx VLAN frame lower */
51 	u32	rx_vlan_u;	/* Rx VLAN frame upper */
52 	u32	rx_vlan_l;	/* Rx VLAN frame lower */
53 	u32	tx_oct_u;	/* Tx octets upper */
54 	u32	tx_oct_l;	/* Tx octets lower */
55 	u32	rx_oct_u;	/* Rx octets upper */
56 	u32	rx_oct_l;	/* Rx octets lower */
57 	u32	rx_uni_u;	/* Rx unicast frame upper */
58 	u32	rx_uni_l;	/* Rx unicast frame lower */
59 	u32	rx_multi_u;	/* Rx multicast frame upper */
60 	u32	rx_multi_l;	/* Rx multicast frame lower */
61 	u32	rx_brd_u;	/* Rx broadcast frame upper */
62 	u32	rx_brd_l;	/* Rx broadcast frame lower */
63 	u32	tx_frame_err_u;	/* Tx frame error upper */
64 	u32	tx_frame_err_l;	/* Tx frame error lower */
65 	u32	tx_uni_u;	/* Tx unicast frame upper */
66 	u32	tx_uni_l;	/* Tx unicast frame lower */
67 	u32	tx_multi_u;	/* Tx multicast frame upper */
68 	u32	tx_multi_l;	/* Tx multicast frame lower */
69 	u32	tx_brd_u;	/* Tx broadcast frame upper */
70 	u32	tx_brd_l;	/* Tx broadcast frame lower */
71 	u32	rx_drop_u;	/* Rx dropped packets upper */
72 	u32	rx_drop_l;	/* Rx dropped packets lower */
73 	u32	rx_eoct_u;	/* Rx ethernet octets upper */
74 	u32	rx_eoct_l;	/* Rx ethernet octets lower */
75 	u32	rx_pkt_u;	/* Rx packets upper */
76 	u32	rx_pkt_l;	/* Rx packets lower */
77 	u32	tx_undsz_u;	/* Undersized packet upper */
78 	u32	tx_undsz_l;	/* Undersized packet lower */
79 	u32	rx_64_u;	/* Rx 64 oct packet upper */
80 	u32	rx_64_l;	/* Rx 64 oct packet lower */
81 	u32	rx_127_u;	/* Rx 65 to 127 oct packet upper */
82 	u32	rx_127_l;	/* Rx 65 to 127 oct packet lower */
83 	u32	rx_255_u;	/* Rx 128 to 255 oct packet upper */
84 	u32	rx_255_l;	/* Rx 128 to 255 oct packet lower */
85 	u32	rx_511_u;	/* Rx 256 to 511 oct packet upper */
86 	u32	rx_511_l;	/* Rx 256 to 511 oct packet lower */
87 	u32	rx_1023_u;	/* Rx 512 to 1023 oct packet upper */
88 	u32	rx_1023_l;	/* Rx 512 to 1023 oct packet lower */
89 	u32	rx_1518_u;	/* Rx 1024 to 1518 oct packet upper */
90 	u32	rx_1518_l;	/* Rx 1024 to 1518 oct packet lower */
91 	u32	rx_1519_u;	/* Rx 1519 to max oct packet upper */
92 	u32	rx_1519_l;	/* Rx 1519 to max oct packet lower */
93 	u32	tx_oversz_u;	/* oversized packet upper */
94 	u32	tx_oversz_l;	/* oversized packet lower */
95 	u32	tx_jabber_u;	/* Jabber packet upper */
96 	u32	tx_jabber_l;	/* Jabber packet lower */
97 	u32	tx_frag_u;	/* Fragment packet upper */
98 	u32	tx_frag_l;	/* Fragment packet lower */
99 	u32	rx_err_u;	/* Rx frame error upper */
100 	u32	rx_err_l;	/* Rx frame error lower */
101 	u32	res5[0x39a];