Lines Matching +full:tx +full:- +full:rx
1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Roy Zang <tie-fei.zang@freescale.com>
16 u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */
17 u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */
23 u32 tx_ipg_length; /* Transmitter inter-packet-gap register */
27 u32 cl_pause_quanta[4]; /* CL01-CL67 pause quanta register */
28 u32 cl_pause_thresh[4]; /* CL01-CL67 pause thresh register */
39 u32 rx_eoct_l; /* Rx ethernet octests lower */
40 u32 rx_eoct_u; /* Rx ethernet octests upper */
41 u32 rx_oct_l; /* Rx octests lower */
42 u32 rx_oct_u; /* Rx octests upper */
43 u32 rx_align_err_l; /* Rx alignment error lower */
44 u32 rx_align_err_u; /* Rx alignment error upper */
45 u32 rx_pause_frame_l; /* Rx valid pause frame upper */
46 u32 rx_pause_frame_u; /* Rx valid pause frame upper */
47 u32 rx_frame_l; /* Rx frame counter lower */
48 u32 rx_frame_u; /* Rx frame counter upper */
49 u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */
50 u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */
51 u32 rx_vlan_l; /* Rx VLAN frame lower */
52 u32 rx_vlan_u; /* Rx VLAN frame upper */
53 u32 rx_err_l; /* Rx frame error lower */
54 u32 rx_err_u; /* Rx frame error upper */
55 u32 rx_uni_l; /* Rx unicast frame lower */
56 u32 rx_uni_u; /* Rx unicast frame upper */
57 u32 rx_multi_l; /* Rx multicast frame lower */
58 u32 rx_multi_u; /* Rx multicast frame upper */
59 u32 rx_brd_l; /* Rx broadcast frame lower */
60 u32 rx_brd_u; /* Rx broadcast frame upper */
61 u32 rx_drop_l; /* Rx dropped packets lower */
62 u32 rx_drop_u; /* Rx dropped packets upper */
63 u32 rx_pkt_l; /* Rx packets lower */
64 u32 rx_pkt_u; /* Rx packets upper */
65 u32 rx_undsz_l; /* Rx undersized packet lower */
66 u32 rx_undsz_u; /* Rx undersized packet upper */
67 u32 rx_64_l; /* Rx 64 oct packet lower */
68 u32 rx_64_u; /* Rx 64 oct packet upper */
69 u32 rx_127_l; /* Rx 65 to 127 oct packet lower */
70 u32 rx_127_u; /* Rx 65 to 127 oct packet upper */
71 u32 rx_255_l; /* Rx 128 to 255 oct packet lower */
72 u32 rx_255_u; /* Rx 128 to 255 oct packet upper */
73 u32 rx_511_l; /* Rx 256 to 511 oct packet lower */
74 u32 rx_511_u; /* Rx 256 to 511 oct packet upper */
75 u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */
76 u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */
77 u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */
78 u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */
79 u32 rx_1519_l; /* Rx 1519 to max oct packet lower */
80 u32 rx_1519_u; /* Rx 1519 to max oct packet upper */
81 u32 rx_oversz_l; /* Rx oversized packet lower */
82 u32 rx_oversz_u; /* Rx oversized packet upper */
83 u32 rx_jabber_l; /* Rx Jabber packet lower */
84 u32 rx_jabber_u; /* Rx Jabber packet upper */
85 u32 rx_frag_l; /* Rx Fragment packet lower */
86 u32 rx_frag_u; /* Rx Fragment packet upper */
87 u32 rx_cnp_l; /* Rx control packet lower */
88 u32 rx_cnp_u; /* Rx control packet upper */
89 u32 rx_drntp_l; /* Rx dripped not truncated packet lower */
90 u32 rx_drntp_u; /* Rx dripped not truncated packet upper */
93 u32 tx_eoct_l; /* Tx ethernet octests lower */
94 u32 tx_eoct_u; /* Tx ethernet octests upper */
95 u32 tx_oct_l; /* Tx octests lower */
96 u32 tx_oct_u; /* Tx octests upper */
98 u32 tx_pause_frame_l; /* Tx valid pause frame lower */
99 u32 tx_pause_frame_u; /* Tx valid pause frame upper */
100 u32 tx_frame_l; /* Tx frame counter lower */
101 u32 tx_frame_u; /* Tx frame counter upper */
102 u32 tx_frame_crc_err_l; /* Tx frame check sequence error lower */
103 u32 tx_frame_crc_err_u; /* Tx frame check sequence error upper */
104 u32 tx_vlan_l; /* Tx VLAN frame lower */
105 u32 tx_vlan_u; /* Tx VLAN frame upper */
106 u32 tx_frame_err_l; /* Tx frame error lower */
107 u32 tx_frame_err_u; /* Tx frame error upper */
108 u32 tx_uni_l; /* Tx unicast frame lower */
109 u32 tx_uni_u; /* Tx unicast frame upper */
110 u32 tx_multi_l; /* Tx multicast frame lower */
111 u32 tx_multi_u; /* Tx multicast frame upper */
112 u32 tx_brd_l; /* Tx broadcast frame lower */
113 u32 tx_brd_u; /* Tx broadcast frame upper */
115 u32 tx_pkt_l; /* Tx packets lower */
116 u32 tx_pkt_u; /* Tx packets upper */
117 u32 tx_undsz_l; /* Tx undersized packet lower */
118 u32 tx_undsz_u; /* Tx undersized packet upper */
119 u32 tx_64_l; /* Tx 64 oct packet lower */
120 u32 tx_64_u; /* Tx 64 oct packet upper */
121 u32 tx_127_l; /* Tx 65 to 127 oct packet lower */
122 u32 tx_127_u; /* Tx 65 to 127 oct packet upper */
123 u32 tx_255_l; /* Tx 128 to 255 oct packet lower */
124 u32 tx_255_u; /* Tx 128 to 255 oct packet upper */
125 u32 tx_511_l; /* Tx 256 to 511 oct packet lower */
126 u32 tx_511_u; /* Tx 256 to 511 oct packet upper */
127 u32 tx_1023_l; /* Tx 512 to 1023 oct packet lower */
128 u32 tx_1023_u; /* Tx 512 to 1023 oct packet upper */
129 u32 tx_1518_l; /* Tx 1024 to 1518 oct packet lower */
130 u32 tx_1518_u; /* Tx 1024 to 1518 oct packet upper */
131 u32 tx_1519_l; /* Tx 1519 to max oct packet lower */
132 u32 tx_1519_u; /* Tx 1519 to max oct packet upper */
134 u32 tx_cnp_l; /* Tx control packet lower */
135 u32 tx_cnp_u; /* Tx control packet upper */
150 u32 hgrx_pause_status; /* HiGig2 rx pause quanta status */
152 u32 rhm; /* Rx HiGig2 message counter register */
153 u32 thm;/* Tx HiGig2 message counter register */
157 /* COMMAND_CONFIG - command and configuration register */
158 #define MEMAC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */
159 #define MEMAC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */
163 /* HASHTABLE_CTRL - Hashtable control register */
164 #define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */
167 /* TX_IPG_LENGTH - Transmit inter-packet gap length register */
170 /* IMASK - interrupt mask register */
175 #define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */
176 #define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */
177 #define IMASK_TX_ER 0x00000200 /* Tx frame error mask */
178 #define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */
179 #define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */
180 #define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */
181 #define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */
182 #define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */
183 #define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */
184 #define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */
185 #define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */
186 #define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */
190 /* IEVENT - interrupt event register */
195 #define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */
196 #define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */
197 #define IEVENT_TX_ER 0x00000200 /* Tx frame error */
198 #define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */
199 #define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */
200 #define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */
201 #define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */
202 #define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */
203 #define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */
204 #define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */
205 #define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */
206 #define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */
210 /* IF_MODE - Interface Mode Register */
211 #define IF_MODE_EN_AUTO 0x00008000 /* 1 - Enable automatic speed selection */
212 #define IF_MODE_SETSP_100M 0x00000000 /* 00 - 100Mbps RGMII */
213 #define IF_MODE_SETSP_10M 0x00002000 /* 01 - 10Mbps RGMII */
214 #define IF_MODE_SETSP_1000M 0x00004000 /* 10 - 1000Mbps RGMII */
216 #define IF_MODE_XGMII 0x00000000 /* 00- XGMII(10) interface mode */
217 #define IF_MODE_GMII 0x00000002 /* 10- GMII interface mode */
219 #define IF_MODE_RG 0x00000004 /* 1- RGMII */
220 #define IF_MODE_RM 0x00000008 /* 1- RGMII */
224 /* Internal PHY Registers - SGMII */