u-boot/include/fsl_memac.h

93 	u32	tx_eoct_l;	/* Tx ethernet octests lower */
94 	u32	tx_eoct_u;	/* Tx ethernet octests upper */
95 	u32	tx_oct_l;	/* Tx octests lower */
96 	u32	tx_oct_u;	/* Tx octests upper */
98 	u32	tx_pause_frame_l; /* Tx valid pause frame lower */
99 	u32	tx_pause_frame_u; /* Tx valid pause frame upper */
100 	u32	tx_frame_l;	/* Tx frame counter lower */
101 	u32	tx_frame_u;	/* Tx frame counter upper */
102 	u32	tx_frame_crc_err_l; /* Tx frame check sequence error lower */
103 	u32	tx_frame_crc_err_u; /* Tx frame check sequence error upper */
104 	u32	tx_vlan_l;	/* Tx VLAN frame lower */
105 	u32	tx_vlan_u;	/* Tx VLAN frame upper */
106 	u32	tx_frame_err_l;	/* Tx frame error lower */
107 	u32	tx_frame_err_u;	/* Tx frame error upper */
108 	u32	tx_uni_l;	/* Tx unicast frame lower */
109 	u32	tx_uni_u;	/* Tx unicast frame upper */
110 	u32	tx_multi_l;	/* Tx multicast frame lower */
111 	u32	tx_multi_u;	/* Tx multicast frame upper */
112 	u32	tx_brd_l;	/* Tx broadcast frame lower */
113 	u32	tx_brd_u;	/* Tx broadcast frame upper */
115 	u32	tx_pkt_l;	/* Tx packets lower */
116 	u32	tx_pkt_u;	/* Tx packets upper */
117 	u32	tx_undsz_l;	/* Tx undersized packet lower */
118 	u32	tx_undsz_u;	/* Tx undersized packet upper */
119 	u32	tx_64_l;	/* Tx 64 oct packet lower */
120 	u32	tx_64_u;	/* Tx 64 oct packet upper */
121 	u32	tx_127_l;	/* Tx 65 to 127 oct packet lower */
122 	u32	tx_127_u;	/* Tx 65 to 127 oct packet upper */
123 	u32	tx_255_l;	/* Tx 128 to 255 oct packet lower */
124 	u32	tx_255_u;	/* Tx 128 to 255 oct packet upper */
125 	u32	tx_511_l;	/* Tx 256 to 511 oct packet lower */
126 	u32	tx_511_u;	/* Tx 256 to 511 oct packet upper */
127 	u32	tx_1023_l;	/* Tx 512 to 1023 oct packet lower */
128 	u32	tx_1023_u;	/* Tx 512 to 1023 oct packet upper */
129 	u32	tx_1518_l;	/* Tx 1024 to 1518 oct packet lower */
130 	u32	tx_1518_u;	/* Tx 1024 to 1518 oct packet upper */
131 	u32	tx_1519_l;	/* Tx 1519 to max oct packet lower */
132 	u32	tx_1519_u;	/* Tx 1519 to max oct packet upper */
134 	u32	tx_cnp_l;	/* Tx control packet lower */
135 	u32	tx_cnp_u;	/* Tx control packet upper */
153 	u32 thm;/* Tx HiGig2 message counter register */
159 #define MEMAC_CMD_CFG_TX_EN		0x00000001 /* MAC Tx path enable */
175 #define IMASK_TX_ECC_ER		0x00001000 /* Tx frame ECC error mask */
176 #define IMASK_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow mask */
177 #define IMASK_TX_ER		0x00000200 /* Tx frame error mask */
195 #define IEVENT_TX_ECC_ER	0x00001000 /* Tx frame ECC error */
196 #define IEVENT_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow */
197 #define IEVENT_TX_ER		0x00000200 /* Tx frame error */