Lines Matching +full:inter +full:- +full:data
1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Roy Zang <tie-fei.zang@freescale.com>
16 u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */
17 u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */
23 u32 tx_ipg_length; /* Transmitter inter-packet-gap register */
27 u32 cl_pause_quanta[4]; /* CL01-CL67 pause quanta register */
28 u32 cl_pause_thresh[4]; /* CL01-CL67 pause thresh register */
157 /* COMMAND_CONFIG - command and configuration register */
163 /* HASHTABLE_CTRL - Hashtable control register */
167 /* TX_IPG_LENGTH - Transmit inter-packet gap length register */
170 /* IMASK - interrupt mask register */
190 /* IEVENT - interrupt event register */
210 /* IF_MODE - Interface Mode Register */
211 #define IF_MODE_EN_AUTO 0x00008000 /* 1 - Enable automatic speed selection */
212 #define IF_MODE_SETSP_100M 0x00000000 /* 00 - 100Mbps RGMII */
213 #define IF_MODE_SETSP_10M 0x00002000 /* 01 - 10Mbps RGMII */
214 #define IF_MODE_SETSP_1000M 0x00004000 /* 10 - 1000Mbps RGMII */
216 #define IF_MODE_XGMII 0x00000000 /* 00- XGMII(10) interface mode */
217 #define IF_MODE_GMII 0x00000002 /* 10- GMII interface mode */
219 #define IF_MODE_RG 0x00000004 /* 1- RGMII */
220 #define IF_MODE_RM 0x00000008 /* 1- RGMII */
224 /* Internal PHY Registers - SGMII */
237 u32 mdio_data; /* MDIO data */