u-boot/include/fsl_memac.h

12 struct memac {  struct
14 	u32	res_0[2];
38 	/* memac statistics counter registers */  argument
39 	u32	rx_eoct_l;	/* Rx ethernet octests lower */
40 	u32	rx_eoct_u;	/* Rx ethernet octests upper */
41 	u32	rx_oct_l;	/* Rx octests lower */
42 	u32	rx_oct_u;	/* Rx octests upper */
43 	u32	rx_align_err_l;	/* Rx alignment error lower */
44 	u32	rx_align_err_u;	/* Rx alignment error upper */
45 	u32	rx_pause_frame_l; /* Rx valid pause frame upper */
46 	u32	rx_pause_frame_u; /* Rx valid pause frame upper */
47 	u32	rx_frame_l;	/* Rx frame counter lower */
48 	u32	rx_frame_u;	/* Rx frame counter upper */
49 	u32	rx_frame_crc_err_l; /* Rx frame check sequence error lower */
50 	u32	rx_frame_crc_err_u; /* Rx frame check sequence error upper */
51 	u32	rx_vlan_l;	/* Rx VLAN frame lower */
52 	u32	rx_vlan_u;	/* Rx VLAN frame upper */
53 	u32	rx_err_l;	/* Rx frame error lower */
54 	u32	rx_err_u;	/* Rx frame error upper */
55 	u32	rx_uni_l;	/* Rx unicast frame lower */
56 	u32	rx_uni_u;	/* Rx unicast frame upper */
57 	u32	rx_multi_l;	/* Rx multicast frame lower */
58 	u32	rx_multi_u;	/* Rx multicast frame upper */
59 	u32	rx_brd_l;	/* Rx broadcast frame lower */
60 	u32	rx_brd_u;	/* Rx broadcast frame upper */
61 	u32	rx_drop_l;	/* Rx dropped packets lower */
62 	u32	rx_drop_u;	/* Rx dropped packets upper */
63 	u32	rx_pkt_l;	/* Rx packets lower */
64 	u32	rx_pkt_u;	/* Rx packets upper */
65 	u32	rx_undsz_l;	/* Rx undersized packet lower */
66 	u32	rx_undsz_u;	/* Rx undersized packet upper */
67 	u32	rx_64_l;	/* Rx 64 oct packet lower */
68 	u32	rx_64_u;	/* Rx 64 oct packet upper */
69 	u32	rx_127_l;	/* Rx 65 to 127 oct packet lower */
70 	u32	rx_127_u;	/* Rx 65 to 127 oct packet upper */
71 	u32	rx_255_l;	/* Rx 128 to 255 oct packet lower */
72 	u32	rx_255_u;	/* Rx 128 to 255 oct packet upper */
73 	u32	rx_511_l;	/* Rx 256 to 511 oct packet lower */
74 	u32	rx_511_u;	/* Rx 256 to 511 oct packet upper */
75 	u32	rx_1023_l;	/* Rx 512 to 1023 oct packet lower */
76 	u32	rx_1023_u;	/* Rx 512 to 1023 oct packet upper */
77 	u32	rx_1518_l;	/* Rx 1024 to 1518 oct packet lower */
78 	u32	rx_1518_u;	/* Rx 1024 to 1518 oct packet upper */
79 	u32	rx_1519_l;	/* Rx 1519 to max oct packet lower */
80 	u32	rx_1519_u;	/* Rx 1519 to max oct packet upper */
81 	u32	rx_oversz_l;	/* Rx oversized packet lower */
82 	u32	rx_oversz_u;	/* Rx oversized packet upper */
83 	u32	rx_jabber_l;	/* Rx Jabber packet lower */
84 	u32	rx_jabber_u;	/* Rx Jabber packet upper */
85 	u32	rx_frag_l;	/* Rx Fragment packet lower */
86 	u32	rx_frag_u;	/* Rx Fragment packet upper */
87 	u32	rx_cnp_l;	/* Rx control packet lower */
88 	u32	rx_cnp_u;	/* Rx control packet upper */
89 	u32	rx_drntp_l;	/* Rx dripped not truncated packet lower */
90 	u32	rx_drntp_u;	/* Rx dripped not truncated packet upper */
91 	u32	res_1d0[0xc];
93 	u32	tx_eoct_l;	/* Tx ethernet octests lower */
94 	u32	tx_eoct_u;	/* Tx ethernet octests upper */
95 	u32	tx_oct_l;	/* Tx octests lower */
96 	u32	tx_oct_u;	/* Tx octests upper */
97 	u32	res_210[0x2];
98 	u32	tx_pause_frame_l; /* Tx valid pause frame lower */
99 	u32	tx_pause_frame_u; /* Tx valid pause frame upper */
100 	u32	tx_frame_l;	/* Tx frame counter lower */
101 	u32	tx_frame_u;	/* Tx frame counter upper */
102 	u32	tx_frame_crc_err_l; /* Tx frame check sequence error lower */
103 	u32	tx_frame_crc_err_u; /* Tx frame check sequence error upper */
104 	u32	tx_vlan_l;	/* Tx VLAN frame lower */
105 	u32	tx_vlan_u;	/* Tx VLAN frame upper */
106 	u32	tx_frame_err_l;	/* Tx frame error lower */
107 	u32	tx_frame_err_u;	/* Tx frame error upper */
108 	u32	tx_uni_l;	/* Tx unicast frame lower */
109 	u32	tx_uni_u;	/* Tx unicast frame upper */
110 	u32	tx_multi_l;	/* Tx multicast frame lower */
111 	u32	tx_multi_u;	/* Tx multicast frame upper */
112 	u32	tx_brd_l;	/* Tx broadcast frame lower */
113 	u32	tx_brd_u;	/* Tx broadcast frame upper */
114 	u32	res_258[0x2];
115 	u32	tx_pkt_l;	/* Tx packets lower */
116 	u32	tx_pkt_u;	/* Tx packets upper */
117 	u32	tx_undsz_l;	/* Tx undersized packet lower */
118 	u32	tx_undsz_u;	/* Tx undersized packet upper */
119 	u32	tx_64_l;	/* Tx 64 oct packet lower */
120 	u32	tx_64_u;	/* Tx 64 oct packet upper */
121 	u32	tx_127_l;	/* Tx 65 to 127 oct packet lower */
122 	u32	tx_127_u;	/* Tx 65 to 127 oct packet upper */
123 	u32	tx_255_l;	/* Tx 128 to 255 oct packet lower */
124 	u32	tx_255_u;	/* Tx 128 to 255 oct packet upper */
125 	u32	tx_511_l;	/* Tx 256 to 511 oct packet lower */
126 	u32	tx_511_u;	/* Tx 256 to 511 oct packet upper */
127 	u32	tx_1023_l;	/* Tx 512 to 1023 oct packet lower */
128 	u32	tx_1023_u;	/* Tx 512 to 1023 oct packet upper */
129 	u32	tx_1518_l;	/* Tx 1024 to 1518 oct packet lower */
130 	u32	tx_1518_u;	/* Tx 1024 to 1518 oct packet upper */
131 	u32	tx_1519_l;	/* Tx 1519 to max oct packet lower */
132 	u32	tx_1519_u;	/* Tx 1519 to max oct packet upper */
133 	u32	res_2a8[0x6];
134 	u32	tx_cnp_l;	/* Tx control packet lower */
135 	u32	tx_cnp_u;	/* Tx control packet upper */
136 	u32	res_2c8[0xe];
139 	u32 if_mode;		/* interface mode control */
140 	u32 if_status;		/* interface status */
141 	u32 res_308[0xe];
144 	u32 hg_config;	/* HiGig2 control and configuration */
145 	u32 res_344[0x3];
146 	u32 hg_pause_quanta;	/* HiGig2 pause quanta */
147 	u32 res_354[0x3];
148 	u32 hg_pause_thresh;	/* HiGig2 pause quanta threshold */
149 	u32 res_364[0x3];
150 	u32 hgrx_pause_status;	/* HiGig2 rx pause quanta status */
151 	u32 hg_fifos_status;	/* HiGig2 fifos status */
152 	u32 rhm;	/* Rx HiGig2 message counter register */
153 	u32 thm;/* Tx HiGig2 message counter register */
154 	u32 res_380[0x320];