Lines Matching full:sdram
33 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */
34 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */
35 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */
36 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */
37 u32 sdram_cfg; /* SDRAM Control Configuration */
38 u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */
39 u32 sdram_mode; /* SDRAM Mode Configuration */
40 u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */
41 u32 sdram_md_cntl; /* SDRAM Mode Control */
42 u32 sdram_interval; /* SDRAM Interval Configuration */
43 u32 sdram_data_init; /* SDRAM Data initialization */
45 u32 sdram_clk_cntl; /* SDRAM Clock Control */
50 u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */
51 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */
52 u32 timing_cfg_6; /* SDRAM Timing Configuration 6 */
53 u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */
69 u32 sdram_mode_3; /* SDRAM Mode Configuration 3 */
70 u32 sdram_mode_4; /* SDRAM Mode Configuration 4 */
71 u32 sdram_mode_5; /* SDRAM Mode Configuration 5 */
72 u32 sdram_mode_6; /* SDRAM Mode Configuration 6 */
73 u32 sdram_mode_7; /* SDRAM Mode Configuration 7 */
74 u32 sdram_mode_8; /* SDRAM Mode Configuration 8 */
76 u32 sdram_mode_9; /* SDRAM Mode Configuration 9 */
77 u32 sdram_mode_10; /* SDRAM Mode Configuration 10 */
78 u32 sdram_mode_11; /* SDRAM Mode Configuration 11 */
79 u32 sdram_mode_12; /* SDRAM Mode Configuration 12 */
80 u32 sdram_mode_13; /* SDRAM Mode Configuration 13 */
81 u32 sdram_mode_14; /* SDRAM Mode Configuration 14 */
82 u32 sdram_mode_15; /* SDRAM Mode Configuration 15 */
83 u32 sdram_mode_16; /* SDRAM Mode Configuration 16 */
85 u32 timing_cfg_8; /* SDRAM Timing Configuration 8 */
86 u32 timing_cfg_9; /* SDRAM Timing Configuration 9 */