Lines Matching +full:chip +full:- +full:select
1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
15 u32 cs0_bnds; /* Chip Select 0 Memory Bounds */
17 u32 cs1_bnds; /* Chip Select 1 Memory Bounds */
19 u32 cs2_bnds; /* Chip Select 2 Memory Bounds */
21 u32 cs3_bnds; /* Chip Select 3 Memory Bounds */
23 u32 cs0_config; /* Chip Select Configuration */
24 u32 cs1_config; /* Chip Select Configuration */
25 u32 cs2_config; /* Chip Select Configuration */
26 u32 cs3_config; /* Chip Select Configuration */
28 u32 cs0_config_2; /* Chip Select Configuration 2 */
29 u32 cs1_config_2; /* Chip Select Configuration 2 */
30 u32 cs2_config_2; /* Chip Select Configuration 2 */
31 u32 cs3_config_2; /* Chip Select Configuration 2 */
63 u8 res_198[0x1a0-0x198];
68 u8 res_1b0[0x200-0x1b0];
75 u8 res_218[0x220-0x218];
84 u8 res_240[0x250-0x240];
87 u8 res_258[0x260-0x258];
89 u8 res_264[0x400-0x264];
94 u8 res_410[0xb20-0x410];
131 u32 err_sbe; /* Single-Bit ECC Error Management */
143 /* CCI-400 registers */
150 u8 res_14[0x100 - 0x14];
152 u8 res_104[0xfd0 - 0x104];
158 u8 res_1008[0x1100 - 0x1008];
161 u8 res_1108[0x110c - 0x1108];
164 u8 res_1114[0x1130 - 0x1114];
168 u8 res_113c[0x2000 - 0x113c];
170 u8 res_6000[0x9004 - 0x6000];
174 u8 res_9010[0xa000 - 0x9010];
176 u32 event_select; /* Event Select */
180 u8 res_a010[0xb000 - 0xa010];
182 u8 res_e004[0x10000 - 0xe004];