Lines Matching +full:0 +full:x000fc000
17 #define FSL_IFC_V1_1_0 0x01010000
18 #define FSL_IFC_V2_0_0 0x02000000
38 #define CSPR_BA 0xFFFF0000
40 #define CSPR_PORT_SIZE 0x00000180
43 #define CSPR_PORT_SIZE_8 0x00000080
45 #define CSPR_PORT_SIZE_16 0x00000100
47 #define CSPR_PORT_SIZE_32 0x00000180
49 #define CSPR_WP 0x00000040
52 #define CSPR_MSEL 0x00000006
55 #define CSPR_MSEL_NOR 0x00000000
57 #define CSPR_MSEL_NAND 0x00000002
59 #define CSPR_MSEL_GPCM 0x00000004
61 #define CSPR_V 0x00000001
62 #define CSPR_V_SHIFT 0
65 #define CSPR_PHYS_ADDR(x) (((uint64_t)x) & 0xffff0000)
70 #define IFC_AMASK_MASK 0xFFFF0000
79 #define CSOR_NAND_ECC_ENC_EN 0x80000000
80 #define CSOR_NAND_ECC_MODE_MASK 0x30000000
82 #define CSOR_NAND_ECC_MODE_4 0x00000000
84 #define CSOR_NAND_ECC_MODE_8 0x10000000
86 #define CSOR_NAND_ECC_DEC_EN 0x04000000
88 #define CSOR_NAND_RAL_MASK 0x01800000
90 #define CSOR_NAND_RAL_1 0x00000000
91 #define CSOR_NAND_RAL_2 0x00800000
92 #define CSOR_NAND_RAL_3 0x01000000
93 #define CSOR_NAND_RAL_4 0x01800000
95 #define CSOR_NAND_PGS_MASK 0x00180000
97 #define CSOR_NAND_PGS_512 0x00000000
98 #define CSOR_NAND_PGS_2K 0x00080000
99 #define CSOR_NAND_PGS_4K 0x00100000
100 #define CSOR_NAND_PGS_8K 0x00180000
102 #define CSOR_NAND_SPRZ_MASK 0x0000E000
104 #define CSOR_NAND_SPRZ_16 0x00000000
105 #define CSOR_NAND_SPRZ_64 0x00002000
106 #define CSOR_NAND_SPRZ_128 0x00004000
107 #define CSOR_NAND_SPRZ_210 0x00006000
108 #define CSOR_NAND_SPRZ_218 0x00008000
109 #define CSOR_NAND_SPRZ_224 0x0000A000
110 #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
112 #define CSOR_NAND_PB_MASK 0x00000700
116 #define CSOR_NAND_TRHZ_MASK 0x0000001C
118 #define CSOR_NAND_TRHZ_20 0x00000000
119 #define CSOR_NAND_TRHZ_40 0x00000004
120 #define CSOR_NAND_TRHZ_60 0x00000008
121 #define CSOR_NAND_TRHZ_80 0x0000000C
122 #define CSOR_NAND_TRHZ_100 0x00000010
124 #define CSOR_NAND_BCTLD 0x00000001
130 #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
132 #define CSOR_NOR_PGRD_EN 0x10000000
134 #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
136 #define CSOR_NOR_ADM_MASK 0x0003E000
140 #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
141 #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
143 #define CSOR_NOR_TRHZ_MASK 0x0000001C
145 #define CSOR_NOR_TRHZ_20 0x00000000
146 #define CSOR_NOR_TRHZ_40 0x00000004
147 #define CSOR_NOR_TRHZ_60 0x00000008
148 #define CSOR_NOR_TRHZ_80 0x0000000C
149 #define CSOR_NOR_TRHZ_100 0x00000010
151 #define CSOR_NOR_BCTLD 0x00000001
157 #define CSOR_GPCM_GPMODE_NORMAL 0x00000000
159 #define CSOR_GPCM_GPMODE_ASIC 0x80000000
161 #define CSOR_GPCM_PARITY_EVEN 0x40000000
163 #define CSOR_GPCM_PAR_EN 0x20000000
165 #define CSOR_GPCM_GPTO_MASK 0x0F000000
169 #define CSOR_GPCM_RGETA_EXT 0x00080000
171 #define CSOR_GPCM_WGETA_EXT 0x00040000
173 #define CSOR_GPCM_ADM_MASK 0x0003E000
177 #define CSOR_GPCM_GAPERRD_MASK 0x00000180
181 #define CSOR_GPCM_TRHZ_MASK 0x0000001C
182 #define CSOR_GPCM_TRHZ_20 0x00000000
183 #define CSOR_GPCM_TRHZ_40 0x00000004
184 #define CSOR_GPCM_TRHZ_60 0x00000008
185 #define CSOR_GPCM_TRHZ_80 0x0000000C
186 #define CSOR_GPCM_TRHZ_100 0x00000010
188 #define CSOR_GPCM_BCTLD 0x00000001
196 #define FTIM0_NAND 0x7EFF3F3F
203 #define FTIM0_NAND_TWH_SHIFT 0
208 #define FTIM1_NAND 0xFFFF3FFF
215 #define FTIM1_NAND_TRP_SHIFT 0
220 #define FTIM2_NAND 0x1FE1F8FF
225 #define FTIM2_NAND_TWHRE_SHIFT 0
230 #define FTIM3_NAND 0xFF000000
237 #define FTIM0_NOR 0xF03F3F3F
244 #define FTIM0_NOR_TEAHC_SHIFT 0
249 #define FTIM1_NOR 0xFF003F3F
254 #define FTIM1_NOR_TSEQRAD_NOR_SHIFT 0
259 #define FTIM2_NOR 0x0F3CFCFF
266 #define FTIM2_NOR_TWP_SHIFT 0
272 #define FTIM0_GPCM 0xF03F3F3F
279 #define FTIM0_GPCM_TEAHC_SHIFT 0
284 #define FTIM1_GPCM 0xFF003F00
292 #define FTIM2_GPCM 0x0F3C00FF
297 #define FTIM2_GPCM_TWP_SHIFT 0
304 #define IFC_RB_STAT_READY_CS0 0x80000000
305 #define IFC_RB_STAT_READY_CS1 0x40000000
306 #define IFC_RB_STAT_READY_CS2 0x20000000
307 #define IFC_RB_STAT_READY_CS3 0x10000000
312 #define IFC_GCR_MASK 0x8000F800
314 #define IFC_GCR_SOFT_RST_ALL 0x80000000
316 #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
323 #define IFC_CM_EVTER_STAT_CSER 0x80000000
329 #define IFC_CM_EVTER_EN_CSEREN 0x80000000
335 #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
338 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
341 #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
342 #define IFC_CM_ERATTR0_ERAID 0x0FF00000
343 #define IFC_CM_ERATTR0_ESRCID 0x0000FF00
348 #define IFC_CCR_MASK 0x0F0F8800
350 #define IFC_CCR_CLK_DIV_MASK 0x0F000000
354 #define IFC_CCR_CLK_DLY_MASK 0x000F0000
358 #define IFC_CCR_INV_CLK_EN 0x00008000
360 #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
366 #define IFC_CSR_CLK_STAT_STABLE 0x80000000
375 #define IFC_NAND_NCFGR_BOOT 0x80000000
377 #define IFC_NAND_SRAM_INIT_EN 0x20000000
379 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
381 #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
383 #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
387 #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
388 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
394 #define IFC_NAND_FCR0_CMD0 0xFF000000
396 #define IFC_NAND_FCR0_CMD1 0x00FF0000
398 #define IFC_NAND_FCR0_CMD2 0x0000FF00
400 #define IFC_NAND_FCR0_CMD3 0x000000FF
401 #define IFC_NAND_FCR0_CMD3_SHIFT 0
402 #define IFC_NAND_FCR1_CMD4 0xFF000000
404 #define IFC_NAND_FCR1_CMD5 0x00FF0000
406 #define IFC_NAND_FCR1_CMD6 0x0000FF00
408 #define IFC_NAND_FCR1_CMD7 0x000000FF
409 #define IFC_NAND_FCR1_CMD7_SHIFT 0
415 #define IFC_NAND_COL_MS 0x80000000
417 #define IFC_NAND_COL_CA_MASK 0x00000FFF
423 #define IFC_NAND_BC 0x000001FF
429 #define IFC_NAND_FIR0_OP0 0xFC000000
431 #define IFC_NAND_FIR0_OP1 0x03F00000
433 #define IFC_NAND_FIR0_OP2 0x000FC000
435 #define IFC_NAND_FIR0_OP3 0x00003F00
437 #define IFC_NAND_FIR0_OP4 0x000000FC
439 #define IFC_NAND_FIR1_OP5 0xFC000000
441 #define IFC_NAND_FIR1_OP6 0x03F00000
443 #define IFC_NAND_FIR1_OP7 0x000FC000
445 #define IFC_NAND_FIR1_OP8 0x00003F00
447 #define IFC_NAND_FIR1_OP9 0x000000FC
449 #define IFC_NAND_FIR2_OP10 0xFC000000
451 #define IFC_NAND_FIR2_OP11 0x03F00000
453 #define IFC_NAND_FIR2_OP12 0x000FC000
455 #define IFC_NAND_FIR2_OP13 0x00003F00
457 #define IFC_NAND_FIR2_OP14 0x000000FC
504 #define IFC_NAND_CSEL 0x0C000000
506 #define IFC_NAND_CSEL_CS0 0x00000000
507 #define IFC_NAND_CSEL_CS1 0x04000000
508 #define IFC_NAND_CSEL_CS2 0x08000000
509 #define IFC_NAND_CSEL_CS3 0x0C000000
515 #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
517 #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
519 #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
521 #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
523 #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
525 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
531 #define IFC_NAND_EVTER_STAT_OPC 0x80000000
533 #define IFC_NAND_EVTER_STAT_FTOER 0x08000000
535 #define IFC_NAND_EVTER_STAT_WPER 0x04000000
537 #define IFC_NAND_EVTER_STAT_ECCER 0x02000000
539 #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
541 #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
543 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
549 #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
550 /* Small Page 0-15 Done */
552 /* Large Page(2K) 0-3 Done */
553 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
554 /* Large Page(4K) 0-1 Done */
555 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
561 #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
563 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
565 #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
567 #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
569 #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
575 #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
577 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
579 #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
581 #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
583 #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
586 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
588 #define IFC_NAND_ERATTR0_MASK 0x0C080000
590 #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
591 #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
592 #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
593 #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
595 #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
601 #define IFC_NAND_NFSR_RS0 0xFF000000
603 #define IFC_NAND_NFSR_RS1 0x00FF0000
608 /* Number of ECC errors on sector n (n = 0-15) */
609 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
611 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
613 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
615 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
616 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
617 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
619 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
621 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
623 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
624 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
625 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
627 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
629 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
631 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
632 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
633 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
635 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
637 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
639 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
640 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
645 #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
653 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
655 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
661 #define IFC_NAND_MDR_RDATA0 0xFF000000
663 #define IFC_NAND_MDR_RDATA1 0x00FF0000
672 #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
674 #define IFC_NOR_EVTER_STAT_WPER 0x04000000
676 #define IFC_NOR_EVTER_STAT_STOER 0x01000000
682 #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
684 #define IFC_NOR_EVTER_EN_WPEREN 0x04000000
686 #define IFC_NOR_EVTER_EN_STOEREN 0x01000000
692 #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
694 #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
696 #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
699 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
702 #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
704 #define IFC_NOR_ERATTR0_ERAID 0x000FF000
706 #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
707 #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
708 #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
709 #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
711 #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
716 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
717 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
722 #define IFC_NORCR_MASK 0x0F0F0000
724 #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
728 #define IFC_NORCR_STOCNT_MASK 0x000F0000
739 #define IFC_GPCM_EVTER_STAT_TOER 0x04000000
741 #define IFC_GPCM_EVTER_STAT_PER 0x01000000
747 #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
749 #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
755 #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
757 #define IFC_GPCM_EEIER_PERIR_EN 0x01000000
760 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
763 #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
765 #define IFC_GPCM_ERATTR0_ERAID 0x000FF000
767 #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
768 #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
769 #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
770 #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
772 #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
778 #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
780 #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
782 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
787 #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
851 u32 res1[0x4];
854 u32 res2[0x8];
870 u32 res10[0x24];
876 u32 res12[0x10];
884 u32 res16[0x2];
886 u32 res17[0x2];
892 u32 res19[0x10];
894 u32 res20[0x1];
896 u32 res21[0x1c];
898 u32 res22[0x2];
902 u32 res24[0x1c];
907 u32 res26[0x3C];
915 u32 res1[0x2];
917 u32 res2[0x2];
919 u32 res3[0x2];
923 u32 res4[0x4];
925 u32 res5[0xEF];
933 u32 res1[0x2];
935 u32 res2[0x2];
937 u32 res3[0x2];
974 u32 res[0x2];
985 u32 res[0x8];
995 u32 res1[0x2];
1008 u32 res7[0x2];
1010 u32 res8[0x2];
1012 u32 res9[0x2];
1014 u32 res10[0x2];
1017 u32 res11[0x2];