Lines Matching defs:fm_bmi_tx_port
135 struct fm_bmi_tx_port { struct
136 u32 fmbm_tcfg; /* Tx configuration */
137 u32 fmbm_tst; /* Tx status */
138 u32 fmbm_tda; /* Tx DMA attributes */
139 u32 fmbm_tfp; /* Tx FIFO parameters */
140 u32 fmbm_tfed; /* Tx frame end data */
141 u32 fmbm_ticp; /* Tx internal context parameters */
142 u32 fmbm_tfne; /* Tx frame next engine */
143 u32 fmbm_tfca; /* Tx frame command attributes */
144 u32 fmbm_tcfqid;/* Tx confirmation frame queue ID */
145 u32 fmbm_tfeqid;/* Tx error frame queue ID */
146 u32 fmbm_tfene; /* Tx frame enqueue next engine */
147 u32 fmbm_trlmts;/* Tx rate limiter scale */
148 u32 fmbm_trlmt; /* Tx rate limiter */
149 u32 res0[0x73];
150 u32 fmbm_tstc; /* Tx statistics counters */
151 u32 fmbm_tfrc; /* Tx frame counter */
152 u32 fmbm_tfdc; /* Tx frames discard counter */
153 u32 fmbm_tfledc;/* Tx frame length error discard counter */
154 u32 fmbm_tfufdc;/* Tx frame unsupported format discard counter */
155 u32 fmbm_tbdc; /* Tx buffers deallocate counter */
156 u32 res1[0x1a];
157 u32 fmbm_tpc; /* Tx performance counters */
158 u32 fmbm_tpcp; /* Tx performance count parameters */
159 u32 fmbm_tccn; /* Tx cycle counter */
160 u32 fmbm_ttuc; /* Tx tasks utilization counter */
161 u32 fmbm_ttcquc;/* Tx transmit confirm queue utilization counter */
162 u32 fmbm_tduc; /* Tx DMA utilization counter */
163 u32 fmbm_tfuc; /* Tx FIFO utilization counter */
164 u32 res2[0x19];
165 u32 fmbm_tdcfg; /* Tx debug configuration */