Lines Matching full:receive
23 u32 rctrl; /* Receive control register */
45 /* transmit and receive counter */
53 /* receive counters */
54 u32 rbyt; /* Receive byte counter */
55 u32 rpkt; /* Receive packet counter */
56 u32 rfcs; /* Receive FCS error */
57 u32 rmca; /* Receive multicast packet */
58 u32 rbca; /* Receive broadcast packet */
59 u32 rxcf; /* Receive control frame */
60 u32 rxpf; /* Receive pause frame */
61 u32 rxuo; /* Receive unknown OP code */
62 u32 raln; /* Receive alignment error */
63 u32 rflr; /* Receive frame length error */
64 u32 rcde; /* Receive code error */
65 u32 rcse; /* Receive carrier sense error */
66 u32 rund; /* Receive undersize packet */
67 u32 rovr; /* Receive oversize packet */
68 u32 rfrg; /* Receive fragments counter */
69 u32 rjbr; /* Receive jabber counter */
70 u32 rdrp; /* Receive drop counter */
122 #define IEVENT_BABR 0x80000000 /* Babbling receive error */
142 #define IMASK_BREN 0x80000000 /* Babbling receive enable */
143 #define IMASK_RXCEN 0x40000000 /* receive control enable */
180 #define TCTRL_RFC_PAUSE 0x00000010 /* Receive flow control pause frame */
182 /* RCTRL - Receive control register */
187 #define RCTRL_RTSE 0x00000040 /* receive 1588 time-stamp enable */
188 #define RCTRL_GRS 0x00000020 /* graceful receive stop */
191 #define RCTRL_RSF 0x00000004 /* receive short frame(17~63 bytes) enable */
197 #define MACCFG1_RST_RXMAC 0x00080000 /* reset receive MAC control block */
199 #define MACCFG1_RST_RXFUN 0x00020000 /* reset receive function block */
202 #define MACCFG1_RX_FLOW 0x00000020 /* Receive flow */
216 #define MACCFG2_PRE_RX_EN 0x00000080 /* receive preamble enable */