Lines Matching +full:half +full:- +full:length

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright 2009-2011 Freescale Semiconductor, Inc.
30 	u32	ipgifg;		/* inter-packet/inter-frame gap */
31 	u32	hafdup;		/* half-duplex control */
63 	u32	rflr;		/* Receive frame length error */
121 /* IEVENT - interrupt events register */
141 /* IMASK - interrupt mask register */
161 /* ECNTRL - ethernet control register */
166 #define ECNTRL_GMIIM	0x00000040 /* 1- GMII or RGMII interface mode */
167 #define ECNTRL_TBIM	0x00000020 /* 1- Ten-bit interface mode */
168 #define ECNTRL_RPM	0x00000010 /* 1- RGMII reduced-pin mode */
169 #define ECNTRL_R100M	0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps
170 				      0- RGMII 10 Mbps, SGMII 10 Mbps */
171 #define ECNTRL_SGMIIM	0x00000002 /* 1- SGMII interface mode */
172 #define ECNTRL_TBIM	0x00000020 /* 1- TBI Interface mode (for SGMII) */
176 /* TCTRL - Transmit control register */
177 #define TCTRL_THDF	0x00000800 /* Transmit half-duplex flow control */
178 #define TCTRL_TTSE	0x00000040 /* Transmit time-stamp enable */
182 /* RCTRL - Receive control register */
183 #define RCTRL_PAL_MASK	0x001f0000 /* packet alignment padding length */
187 #define RCTRL_RTSE	0x00000040 /* receive 1588 time-stamp enable */
195 /* MACCFG1 - MAC configuration 1 register */
210 /* MACCFG2 - MAC configuration 2 register */
211 #define MACCFG2_PRE_LEN_MASK	0x0000f000 /* preamble length */
219 #define MACCFG2_LEN_CHECK	0x00000010 /* MAC check frame's length Rx */