Lines Matching full:unsigned
244 unsigned int bnds;
245 unsigned int config;
246 unsigned int config_2;
248 unsigned int timing_cfg_3;
249 unsigned int timing_cfg_0;
250 unsigned int timing_cfg_1;
251 unsigned int timing_cfg_2;
252 unsigned int ddr_sdram_cfg;
253 unsigned int ddr_sdram_cfg_2;
254 unsigned int ddr_sdram_cfg_3;
255 unsigned int ddr_sdram_mode;
256 unsigned int ddr_sdram_mode_2;
257 unsigned int ddr_sdram_mode_3;
258 unsigned int ddr_sdram_mode_4;
259 unsigned int ddr_sdram_mode_5;
260 unsigned int ddr_sdram_mode_6;
261 unsigned int ddr_sdram_mode_7;
262 unsigned int ddr_sdram_mode_8;
263 unsigned int ddr_sdram_mode_9;
264 unsigned int ddr_sdram_mode_10;
265 unsigned int ddr_sdram_mode_11;
266 unsigned int ddr_sdram_mode_12;
267 unsigned int ddr_sdram_mode_13;
268 unsigned int ddr_sdram_mode_14;
269 unsigned int ddr_sdram_mode_15;
270 unsigned int ddr_sdram_mode_16;
271 unsigned int ddr_sdram_md_cntl;
272 unsigned int ddr_sdram_interval;
273 unsigned int ddr_data_init;
274 unsigned int ddr_sdram_clk_cntl;
275 unsigned int ddr_init_addr;
276 unsigned int ddr_init_ext_addr;
277 unsigned int timing_cfg_4;
278 unsigned int timing_cfg_5;
279 unsigned int timing_cfg_6;
280 unsigned int timing_cfg_7;
281 unsigned int timing_cfg_8;
282 unsigned int timing_cfg_9;
283 unsigned int ddr_zq_cntl;
284 unsigned int ddr_wrlvl_cntl;
285 unsigned int ddr_wrlvl_cntl_2;
286 unsigned int ddr_wrlvl_cntl_3;
287 unsigned int ddr_sr_cntr;
288 unsigned int ddr_sdram_rcw_1;
289 unsigned int ddr_sdram_rcw_2;
290 unsigned int ddr_sdram_rcw_3;
291 unsigned int ddr_sdram_rcw_4;
292 unsigned int ddr_sdram_rcw_5;
293 unsigned int ddr_sdram_rcw_6;
294 unsigned int dq_map_0;
295 unsigned int dq_map_1;
296 unsigned int dq_map_2;
297 unsigned int dq_map_3;
298 unsigned int ddr_eor;
299 unsigned int ddr_cdr1;
300 unsigned int ddr_cdr2;
301 unsigned int err_disable;
302 unsigned int err_int_en;
303 unsigned int debug[64];
307 unsigned int all_dimms_ecc_capable;
308 unsigned int all_dimms_tckmax_ps;
309 unsigned int all_dimms_burst_lengths_bitmask;
310 unsigned int all_dimms_registered;
311 unsigned int all_dimms_unbuffered;
312 /* unsigned int lowest_common_spd_caslat; */
313 unsigned int all_dimms_minimum_trcd_ps;
332 unsigned int registered_dimm_en; /* use registered DIMM support */
336 unsigned int auto_precharge;
337 unsigned int odt_rd_cfg;
338 unsigned int odt_wr_cfg;
339 unsigned int odt_rtt_norm;
340 unsigned int odt_rtt_wr;
344 unsigned int memctl_interleaving;
345 unsigned int memctl_interleaving_mode;
346 unsigned int ba_intlv_ctl;
347 unsigned int addr_hash;
350 unsigned int ecc_mode; /* Use ECC? */
352 unsigned int ecc_init_using_memctl;
353 unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */
355 unsigned int self_refresh_in_sleep;
357 unsigned int self_refresh_interrupt_en;
358 unsigned int dynamic_power; /* DYN_PWR */
360 unsigned int data_bus_width;
361 unsigned int burst_length; /* BL4, OTF and BL8 */
363 unsigned int otf_burst_chop_en;
365 unsigned int mirrored_dimm;
366 unsigned int quad_rank_present;
367 unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */
368 unsigned int x4_en; /* enable x4 devices */
369 unsigned int package_3ds;
372 unsigned int cas_latency_override;
373 unsigned int cas_latency_override_value;
374 unsigned int use_derated_caslat;
375 unsigned int additive_latency_override;
376 unsigned int additive_latency_override_value;
378 unsigned int clk_adjust; /* */
379 unsigned int cpo_override; /* override timing_cfg_2[CPO]*/
380 unsigned int cpo_sample; /* optimize debug_29[24:31] */
381 unsigned int write_data_delay; /* DQS adjust */
383 unsigned int cswl_override;
384 unsigned int wrlvl_override;
385 unsigned int wrlvl_sample; /* Write leveling */
386 unsigned int wrlvl_start;
387 unsigned int wrlvl_ctl_2;
388 unsigned int wrlvl_ctl_3;
390 unsigned int half_strength_driver_enable;
391 unsigned int twot_en;
392 unsigned int threet_en;
393 unsigned int bstopre;
394 unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */
397 unsigned int rtt_override; /* rtt_override enable */
398 unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
399 unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
402 unsigned int auto_self_refresh_en;
403 unsigned int sr_it;
405 unsigned int zq_en;
407 unsigned int wrlvl_en;
409 unsigned int rcw_override;
410 unsigned int rcw_1;
411 unsigned int rcw_2;
412 unsigned int rcw_3;
414 unsigned int ddr_cdr1;
415 unsigned int ddr_cdr2;
417 unsigned int trwt_override;
418 unsigned int trwt; /* read-to-write turnaround */
423 phys_size_t fsl_other_ddr_sdram(unsigned long long base,
424 unsigned int first_ctrl,
425 unsigned int num_ctrls,
426 unsigned int dimm_slots_per_ctrl,
432 unsigned int ctrl_num, int step);
434 void print_ddr_info(unsigned int start_ctrl);
473 extern void ddr_enable_ecc(unsigned int dram_size);