Lines Matching defs:memctl_options_s
324 typedef struct memctl_options_s { struct
332 unsigned int registered_dimm_en; /* use registered DIMM support */
335 struct cs_local_opts_s {
341 } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL];
344 unsigned int memctl_interleaving;
345 unsigned int memctl_interleaving_mode;
346 unsigned int ba_intlv_ctl;
347 unsigned int addr_hash;
350 unsigned int ecc_mode; /* Use ECC? */
352 unsigned int ecc_init_using_memctl;
353 unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */
355 unsigned int self_refresh_in_sleep;
357 unsigned int self_refresh_interrupt_en;
358 unsigned int dynamic_power; /* DYN_PWR */
360 unsigned int data_bus_width;
361 unsigned int burst_length; /* BL4, OTF and BL8 */
363 unsigned int otf_burst_chop_en;
365 unsigned int mirrored_dimm;
366 unsigned int quad_rank_present;
367 unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */
368 unsigned int x4_en; /* enable x4 devices */
369 unsigned int package_3ds;
372 unsigned int cas_latency_override;
373 unsigned int cas_latency_override_value;
374 unsigned int use_derated_caslat;
375 unsigned int additive_latency_override;
376 unsigned int additive_latency_override_value;
378 unsigned int clk_adjust; /* */
379 unsigned int cpo_override; /* override timing_cfg_2[CPO]*/
380 unsigned int cpo_sample; /* optimize debug_29[24:31] */
381 unsigned int write_data_delay; /* DQS adjust */
383 unsigned int cswl_override;
384 unsigned int wrlvl_override;
385 unsigned int wrlvl_sample; /* Write leveling */
386 unsigned int wrlvl_start;
387 unsigned int wrlvl_ctl_2;
388 unsigned int wrlvl_ctl_3;
390 unsigned int half_strength_driver_enable;
391 unsigned int twot_en;
392 unsigned int threet_en;
393 unsigned int bstopre;
394 unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */
397 unsigned int rtt_override; /* rtt_override enable */
398 unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */
399 unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */
402 unsigned int auto_self_refresh_en;
403 unsigned int sr_it;
405 unsigned int zq_en;
407 unsigned int wrlvl_en;
409 unsigned int rcw_override;
410 unsigned int rcw_1;
411 unsigned int rcw_2;
412 unsigned int rcw_3;
414 unsigned int ddr_cdr1;
415 unsigned int ddr_cdr2;
417 unsigned int trwt_override;
418 unsigned int trwt; /* read-to-write turnaround */