include/faraday/ftsdmc021.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
4  * Po-Yu Chuang <ratbert@faraday-tech.com>
11  * FTSDMC021 - SDRAM Controller
18 	unsigned int	tp1;		/* 0x00 - SDRAM Timing Parameter 1 */
19 	unsigned int	tp2;		/* 0x04 - SDRAM Timing Parameter 2 */
20 	unsigned int	cr1;		/* 0x08 - SDRAM Configuration Reg 1 */
21 	unsigned int	cr2;		/* 0x0c - SDRAM Configuration Reg 2 */
22 	unsigned int	bank0_bsr;	/* 0x10 - Ext. Bank Base/Size Reg 0 */
23 	unsigned int	bank1_bsr;	/* 0x14 - Ext. Bank Base/Size Reg 1 */
24 	unsigned int	bank2_bsr;	/* 0x18 - Ext. Bank Base/Size Reg 2 */
25 	unsigned int	bank3_bsr;	/* 0x1c - Ext. Bank Base/Size Reg 3 */
26 	unsigned int	bank4_bsr;	/* 0x20 - Ext. Bank Base/Size Reg 4 */
27 	unsigned int	bank5_bsr;	/* 0x24 - Ext. Bank Base/Size Reg 5 */
28 	unsigned int	bank6_bsr;	/* 0x28 - Ext. Bank Base/Size Reg 6 */
29 	unsigned int	bank7_bsr;	/* 0x2c - Ext. Bank Base/Size Reg 7 */
30 	unsigned int	ragr;		/* 0x30 - Read Arbitration Group Reg */
31 	unsigned int	frr;		/* 0x34 - Flush Request Register */
32 	unsigned int	ebisr;		/* 0x38 - EBI Support Register	*/
33 	unsigned int	rsved[25];	/* 0x3c-0x9c - Reserved		*/
34 	unsigned int	crr;		/* 0x100 - Controller Revision Reg */
35 	unsigned int	cfr;		/* 0x104 - Controller Feature Reg */
43 #define FTSDMC021_TP1_TWR(x)	(((x) & 0x3) << 4)	/* W-Recovery Time */
44 #define FTSDMC021_TP1_TRF(x)	(((x) & 0xf) << 8)	/* Auto-Refresh Cycle */
45 #define FTSDMC021_TP1_TRCD(x)	(((x) & 0x7) << 12)	/* RAS-to-CAS Delay */
53 /* b(16:19) - Initial Refresh Times */
55 /* b(20:23) - Initial Pre-Charge Times */
67 /* The value of b(0:3)CR1: 1M-512M, must be power of 2 */
68 #define FTSDMC021_BANK_SIZE(x)		(ffs(x) - 1)
73 #define FTSDMC021_CR2_SREF	(1 << 0)	/* Self-Refresh Mode */
75 #define FTSDMC021_CR2_ISMR	(1 << 2)	/* Start Set-Mode-Register */
77 #define FTSDMC021_CR2_IPREC	(1 << 4)	/* Init Pre-Charge Start Flag */
85 /* 12-bit base address of external bank.
87  * The 12-bit equals to the haddr[31:20] of AHB address bus. */
111 #define FTSDMC021_EBISR_MR(x)		((x) & 0xfff)	/* Far-end mode	*/
112 #define FTSDMC021_EBISR_PRSMR		(1 << 12)	/* Pre-SMR	*/
114 #define FTSDMC021_EBISR_POSMR		(1 << 14)	/* Post-SMR	*/