dt-bindings/clock/tegra186-clock.h

25  *   @defgroup extern_output external output clocks
349 /** @brief output of gate CLK_ENB_FUSE */
353  * @details output of gate CLK_ENB_GPU. This output connects to the GPU
359 /** @brief output of gate CLK_ENB_PCIE */
361 /** @brief output of the divider IPFS_CLK_DIVISOR */
363 /** @brief output of gate CLK_ENB_PCIE2_IOBIST */
365 /** @brief output of gate CLK_ENB_PCIERX0*/
367 /** @brief output of gate CLK_ENB_PCIERX1*/
369 /** @brief output of gate CLK_ENB_PCIERX2*/
371 /** @brief output of gate CLK_ENB_PCIERX3*/
373 /** @brief output of gate CLK_ENB_PCIERX4*/
375 /** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
377 /** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
379 /** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
381 /** @brief output of gate CLK_ENB_SOR_SAFE */
383 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
385 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
387 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
389 /** @brief output of gate CLK_ENB_SPDIF_DOUBLER */
397 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
399 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
401 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
403 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
405 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */
407 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
409 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
411 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
413 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
424 /* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
426 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
428 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
430 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */
432 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
434 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
436 /** output of gate CLK_ENB_DTV */
438 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
440 /** @brief output of gate CLK_ENB_DP2 */
442 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
444 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
446 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
448 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
450 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
452 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
454 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
456 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
458 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
460 /** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
462 /** @brief output of gate CLK_ENB_CEC */
464 /** @brief output of gate CLK_ENB_DPAUX1 */
466 /** @brief output of gate CLK_ENB_DPAUX */
468 /** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
470 /** @brief output of gate CLK_ENB_HDA2HDMICODEC */
472 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */
474 /** @brief output of gate CLK_ENB_SATA_OOB */
476 /** @brief output of gate CLK_ENB_SATA_IOBIST */
478 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */
480 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */
482 /** @brief output of gate CLK_ENB_APB2APE */
484 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
486 /** @brief output of gate CLK_ENB_IQC1 */
488 /** @brief output of gate CLK_ENB_IQC2 */
492 /** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */
494 /** @brief output of gate CLK_ENB_PLLC4_OUT */
496 /** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */
504 /** @brief output of gate CLK_ENB_DSI */
506 /** @brief output of gate CLK_ENB_MIPI_CAL */
508 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */
510 /** @brief output of gate CLK_ENB_DSIB */
512 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */
514 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
516 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
518 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
520 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
522 /**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
524 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
526 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */
528 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
530 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
532 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
534 /** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
536 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */
538 /** @brief output of gate CLK_ENB_HSIC_TRK */
540 /** @brief output of gate CLK_ENB_USB2_TRK */
542 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */
544 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */
546 /** @brief output of gate CLK_ENB_ADSP */
548 /** @brief output of gate CLK_ENB_ADSPNEON */
550 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
552 /** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
554 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
556 /** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
558 /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
560 /** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
562 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */
564 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
566 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
568 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
570 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
572 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
574 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
576 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
578 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
580 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */
582 /** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP…
584 /** @brief output of gate CLK_ENB_NVDISPLAY_DSC */
586 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */
588 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */
590 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */
592 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */
594 /** @brief output of gate CLK_ENB_EQOS */
596 /** @brief output of gate CLK_ENB_EQOS_RX */
598 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
600 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
602 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
604 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
606 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
608 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
610 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */
612 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */
614 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */
616 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
618 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
620 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
622 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
624 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
626 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
628 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
630 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
632 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
636 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */
638 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */
640 /** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */
642 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */
644 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
646 /** @brief output of gate CLK_ENB_CAN1_HOST */
648 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
650 /** @brief output of gate CLK_ENB_CAN2_HOST */
652 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */
654 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
656 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */
658 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
660 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
662 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
664 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */
666 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */
668 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
670 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
672 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */
674 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
676 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read…
678 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */
680 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
682 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */
684 /** @brief output of gate CLK_ENB_DSIC */
686 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */
688 /** @brief output of gate CLK_ENB_DSID */
690 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */
692 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */
694 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */
696 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */
698 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */
700 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */
702 /** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */
704 /** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */
706 /** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */
708 /** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */
710 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
712 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
714 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
716 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
718 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
720 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
722 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
724 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
726 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
728 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
730 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
732 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
734 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
736 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */
738 /** @brief output of gate CLK_ENB_PLLREFE_OUT */
740 /** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 out…
746 /** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */
748 /** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */
752 /** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider …
758 /** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is T…
760 /** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
762 /** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
764 /** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */
766 /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_…
768 /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_…
772 /** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */
774 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */
792 /** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SO…
794 /** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SO…
796 /** @brief fixed /5 divider.  Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used a…
800 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */
802 /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */
808 /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be…
810 /** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC…
814 /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
818  * @details fixed /2 divider. Output frequency is
822 /** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */
824 /** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
840  * @details Note that this clock only controls the VCO output, before
867 /** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */
903 /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
905 /** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */
913 /** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR…
915 /** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR…