u-boot/include/ddr_spd.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Copyright 2008-2014 Freescale Semiconductor, Inc.
10  * Format from "JEDEC Standard No. 21-C,
20 	unsigned char dataw_lsb;   /*  6 Data Width of this assembly */
21 	unsigned char dataw_msb;   /*  7 ... Data Width continuation */
37 	unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time @ CL=X-0.5 */
39 					 Clk @ CL=X-0.5 (tAC) */
40 	unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time @ CL=X-1 */
41 	unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */
43 	unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
49 	unsigned char data_setup;  /* 34 Data Input Setup Time Before Strobe */
50 	unsigned char data_hold;   /* 35 Data Input Hold Time After Strobe */
51 	unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */
52 	unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
53 	unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
59 	unsigned char res_48_61[14]; /* 48-61 Reserved */
60 	unsigned char spd_rev;     /* 62 SPD Data Revision Code */
61 	unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
62 	unsigned char mid[8];      /* 64-71 Mfr's JEDEC ID code per JEP-106 */
68 	unsigned char mspec[27];   /* 99-127 Manufacturer Specific Data */
83 	unsigned char dataw;       /*  6 Module Data Width */
100 	unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time @ CL=X-1 */
101 	unsigned char clk_access2; /* 24 SDRAM Access from Clk @ CL=X-1 (tAC) */
102 	unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time @ CL=X-2 */
103 	unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-2 (tAC) */
105 	unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
111 	unsigned char data_setup;  /* 34 Data Input Setup Time
113 	unsigned char data_hold;   /* 35 Data Input Hold Time
120 	unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
121 	unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
128 					 Top (Case) to Ambient (Psi T-A DRAM) */
130 					 due to Activate-Precharge/Mode Bits
136 					 due to Precharge Power-Down (DT2P) */
138 					 due to Active Standby (DT3N) */
140 					 due to Active Power-Down with
143 					 due to Active Power-Down with Slow
152 					 Auto-Precharge (DT7) */
154 					 Top (Case) to Ambient (Psi T-A PLL) */
157 					 (Psi T-A Register) */
159 					 due to PLL Active (DT PLL Active) */
161 					 Ambient due to Register Active/Mode Bit
162 					 (DT Register Active/Mode Bit) */
163 	unsigned char spd_rev;     /* 62 SPD Data Revision Code */
164 	unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
165 	unsigned char mid[8];      /* 64 Mfr's JEDEC ID code per JEP-106 */
171 	unsigned char mspec[27];   /* 99-127 Manufacturer Specific Data */
176 	/* General Section: Bytes 0-59 */
200 	unsigned char trrd_min;        /* 19 Min Row Active to
201 					     Row Active Delay Time */
204 	unsigned char tras_min_lsb;    /* 22 Min Active to Precharge
206 	unsigned char trc_min_lsb;     /* 23 Min Active to Active/Refresh
226 	unsigned char res_39_59[21];   /* 39-59 Reserved, General Section */
228 	/* Module-Specific Section: Bytes 60-116 */
240 			/* 64-116 (Unbuffered) Reserved */
262 			/* 69-76 RC1,3,5...15 (MS Nibble) / RC0,2,4...14 (LS Nibble) */
265 		unsigned char uc[57]; /* 60-116 Module-Specific Section */
268 	/* Unique Module ID: Bytes 117-125 */
269 	unsigned char mmid_lsb;        /* 117 Module MfgID Code LSB - JEP-106 */
270 	unsigned char mmid_msb;        /* 118 Module MfgID Code MSB - JEP-106 */
272 	unsigned char mdate[2];        /* 120-121 Mfg Date */
273 	unsigned char sernum[4];       /* 122-125 Module Serial Number */
275 	/* CRC: Bytes 126-127 */
276 	unsigned char crc[2];          /* 126-127 SPD CRC */
278 	/* Other Manufacturer Fields and User Space: Bytes 128-255 */
279 	unsigned char mpart[18];       /* 128-145 Mfg's Module Part Number */
280 	unsigned char mrev[2];         /* 146-147 Module Revision Code */
282 	unsigned char dmid_lsb;        /* 148 DRAM MfgID Code LSB - JEP-106 */
283 	unsigned char dmid_msb;        /* 149 DRAM MfgID Code MSB - JEP-106 */
285 	unsigned char msd[26];         /* 150-175 Mfg's Specific Data */
286 	unsigned char cust[80];        /* 176-255 Open for Customer Use */
290 /* From JEEC Standard No. 21-C release 23A */
292 	/* General Section: Bytes 0-127 */
334 	uint8_t res_41[60-41];		/* 41 Rserved */
335 	uint8_t mapping[78-60];		/* 60~77 Connector to SDRAM bit map */
336 	uint8_t res_78[117-78];		/* 78~116, Reserved */
346 	/* CRC: Bytes 126-127 */
347 	uint8_t crc[2];			/* 126-127 SPD CRC */
349 	/* Module-Specific Section: Bytes 128-255 */
362 			uint8_t res_132[254-132];
388 			u8 res_137[254 - 139];
415 			/* 139 Data Buffer Revision Number */
425 			/* 144 Data Buffer VrefDQ for DRAM Interface */
428 			 * 145 Data Buffer MDQ Drive Strength and RTT
429 			 * for data rate <= 1866
433 			 * 146 Data Buffer MDQ Drive Strength and RTT
434 			 * for 1866 < data rate <= 2400
438 			 * 147 Data Buffer MDQ Drive Strength and RTT
439 			 * for 2400 < data rate <= 3200
446 			 * for data rate <= 1866
451 			 * for 1866 < data rate <= 2400
456 			 * for 2400 < data rate <= 3200
461 			 * for data rate <= 1866
466 			 * for 1866 < data rate <= 2400
471 			 * for 2400 < data rate <= 3200
474 			uint8_t res_155[254-155];	/* Reserved */
478 		uint8_t uc[128]; /* 128-255 Module-Specific Section */
481 	uint8_t res_256[320-256];	/* 256~319 Reserved */
483 	/* Module supplier's data: Byte 320~383 */
494 	uint8_t msd[29];		/* 353~381 Mfg's Specific Data */
497 	uint8_t user[512-384];		/* 384~511 End User Programmable */