Lines Matching defs:ddr3_spd_eeprom_s
175 typedef struct ddr3_spd_eeprom_s { struct
177 unsigned char info_size_crc; /* 0 # bytes written into serial memory,
179 unsigned char spd_rev; /* 1 Total # bytes of SPD mem device */
180 unsigned char mem_type; /* 2 Key Byte / Fundamental mem type */
181 unsigned char module_type; /* 3 Key Byte / Module Type */
182 unsigned char density_banks; /* 4 SDRAM Density and Banks */
183 unsigned char addressing; /* 5 SDRAM Addressing */
184 unsigned char module_vdd; /* 6 Module nominal voltage, VDD */
185 unsigned char organization; /* 7 Module Organization */
186 unsigned char bus_width; /* 8 Module Memory Bus Width */
187 unsigned char ftb_div; /* 9 Fine Timebase (FTB)
189 unsigned char mtb_dividend; /* 10 Medium Timebase (MTB) Dividend */
190 unsigned char mtb_divisor; /* 11 Medium Timebase (MTB) Divisor */
191 unsigned char tck_min; /* 12 SDRAM Minimum Cycle Time */
192 unsigned char res_13; /* 13 Reserved */
193 unsigned char caslat_lsb; /* 14 CAS Latencies Supported,
195 unsigned char caslat_msb; /* 15 CAS Latencies Supported,
197 unsigned char taa_min; /* 16 Min CAS Latency Time */
198 unsigned char twr_min; /* 17 Min Write REcovery Time */
199 unsigned char trcd_min; /* 18 Min RAS# to CAS# Delay Time */
200 unsigned char trrd_min; /* 19 Min Row Active to
202 unsigned char trp_min; /* 20 Min Row Precharge Delay Time */
203 unsigned char tras_trc_ext; /* 21 Upper Nibbles for tRAS and tRC */
204 unsigned char tras_min_lsb; /* 22 Min Active to Precharge
206 unsigned char trc_min_lsb; /* 23 Min Active to Active/Refresh
208 unsigned char trfc_min_lsb; /* 24 Min Refresh Recovery Delay Time */
209 unsigned char trfc_min_msb; /* 25 Min Refresh Recovery Delay Time */
210 unsigned char twtr_min; /* 26 Min Internal Write to
212 unsigned char trtp_min; /* 27 Min Internal Read to Precharge
214 unsigned char tfaw_msb; /* 28 Upper Nibble for tFAW */
215 unsigned char tfaw_min; /* 29 Min Four Activate Window
217 unsigned char opt_features; /* 30 SDRAM Optional Features */
218 unsigned char therm_ref_opt; /* 31 SDRAM Thermal and Refresh Opts */
219 unsigned char therm_sensor; /* 32 Module Thermal Sensor */
220 unsigned char device_type; /* 33 SDRAM device type */
221 int8_t fine_tck_min; /* 34 Fine offset for tCKmin */
222 int8_t fine_taa_min; /* 35 Fine offset for tAAmin */
223 int8_t fine_trcd_min; /* 36 Fine offset for tRCDmin */
224 int8_t fine_trp_min; /* 37 Fine offset for tRPmin */
225 int8_t fine_trc_min; /* 38 Fine offset for tRCmin */
226 unsigned char res_39_59[21]; /* 39-59 Reserved, General Section */
229 union {
266 } mod_section;
269 unsigned char mmid_lsb; /* 117 Module MfgID Code LSB - JEP-106 */
270 unsigned char mmid_msb; /* 118 Module MfgID Code MSB - JEP-106 */
271 unsigned char mloc; /* 119 Mfg Location */
272 unsigned char mdate[2]; /* 120-121 Mfg Date */
273 unsigned char sernum[4]; /* 122-125 Module Serial Number */
276 unsigned char crc[2]; /* 126-127 SPD CRC */
279 unsigned char mpart[18]; /* 128-145 Mfg's Module Part Number */
280 unsigned char mrev[2]; /* 146-147 Module Revision Code */
282 unsigned char dmid_lsb; /* 148 DRAM MfgID Code LSB - JEP-106 */
283 unsigned char dmid_msb; /* 149 DRAM MfgID Code MSB - JEP-106 */
285 unsigned char msd[26]; /* 150-175 Mfg's Specific Data */
286 unsigned char cust[80]; /* 176-255 Open for Customer Use */