u-boot/include/ddr_spd.h

13 typedef struct ddr1_spd_eeprom_s {  struct
14 	unsigned char info_size;   /*  0 # bytes written into serial memory */
15 	unsigned char chip_size;   /*  1 Total # bytes of SPD memory device */
16 	unsigned char mem_type;    /*  2 Fundamental memory type */
17 	unsigned char nrow_addr;   /*  3 # of Row Addresses on this assembly */
18 	unsigned char ncol_addr;   /*  4 # of Column Addrs on this assembly */
19 	unsigned char nrows;       /*  5 Number of DIMM Banks */
20 	unsigned char dataw_lsb;   /*  6 Data Width of this assembly */
21 	unsigned char dataw_msb;   /*  7 ... Data Width continuation */
22 	unsigned char voltage;     /*  8 Voltage intf std of this assembly */
23 	unsigned char clk_cycle;   /*  9 SDRAM Cycle time @ CL=X */
24 	unsigned char clk_access;  /* 10 SDRAM Access from Clk @ CL=X (tAC) */
25 	unsigned char config;      /* 11 DIMM Configuration type */
26 	unsigned char refresh;     /* 12 Refresh Rate/Type */
27 	unsigned char primw;       /* 13 Primary SDRAM Width */
28 	unsigned char ecw;         /* 14 Error Checking SDRAM width */
29 	unsigned char min_delay;   /* 15 for Back to Back Random Address */
30 	unsigned char burstl;      /* 16 Burst Lengths Supported */
31 	unsigned char nbanks;      /* 17 # of Banks on SDRAM Device */
32 	unsigned char cas_lat;     /* 18 CAS# Latencies Supported */
33 	unsigned char cs_lat;      /* 19 CS# Latency */
34 	unsigned char write_lat;   /* 20 Write Latency (aka Write Recovery) */
35 	unsigned char mod_attr;    /* 21 SDRAM Module Attributes */
36 	unsigned char dev_attr;    /* 22 SDRAM Device Attributes */
37 	unsigned char clk_cycle2;  /* 23 Min SDRAM Cycle time @ CL=X-0.5 */
38 	unsigned char clk_access2; /* 24 SDRAM Access from
40 	unsigned char clk_cycle3;  /* 25 Min SDRAM Cycle time @ CL=X-1 */
41 	unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */
42 	unsigned char trp;         /* 27 Min Row Precharge Time (tRP)*/
43 	unsigned char trrd;        /* 28 Min Row Active to Row Active (tRRD) */
44 	unsigned char trcd;        /* 29 Min RAS to CAS Delay (tRCD) */
45 	unsigned char tras;        /* 30 Minimum RAS Pulse Width (tRAS) */
46 	unsigned char bank_dens;   /* 31 Density of each bank on module */
47 	unsigned char ca_setup;    /* 32 Addr + Cmd Setup Time Before Clk */
48 	unsigned char ca_hold;     /* 33 Addr + Cmd Hold Time After Clk */
49 	unsigned char data_setup;  /* 34 Data Input Setup Time Before Strobe */
50 	unsigned char data_hold;   /* 35 Data Input Hold Time After Strobe */
51 	unsigned char res_36_40[5];/* 36-40 reserved for VCSDRAM */
52 	unsigned char trc;         /* 41 Min Active to Auto refresh time tRC */
53 	unsigned char trfc;        /* 42 Min Auto to Active period tRFC */
54 	unsigned char tckmax;      /* 43 Max device cycle time tCKmax */
55 	unsigned char tdqsq;       /* 44 Max DQS to DQ skew (tDQSQ max) */
56 	unsigned char tqhs;        /* 45 Max Read DataHold skew (tQHS) */
57 	unsigned char res_46;      /* 46 Reserved */
58 	unsigned char dimm_height; /* 47 DDR SDRAM DIMM Height */
59 	unsigned char res_48_61[14]; /* 48-61 Reserved */
60 	unsigned char spd_rev;     /* 62 SPD Data Revision Code */
61 	unsigned char cksum;       /* 63 Checksum for bytes 0-62 */
62 	unsigned char mid[8];      /* 64-71 Mfr's JEDEC ID code per JEP-106 */
63 	unsigned char mloc;        /* 72 Manufacturing Location */
64 	unsigned char mpart[18];   /* 73 Manufacturer's Part Number */
65 	unsigned char rev[2];      /* 91 Revision Code */
66 	unsigned char mdate[2];    /* 93 Manufacturing Date */
67 	unsigned char sernum[4];   /* 95 Assembly Serial Number */
68 	unsigned char mspec[27];   /* 99-127 Manufacturer Specific Data */