Lines Matching +full:0 +full:xa000000
24 # define CONFIG_MACH_TYPE_COMPAT_REV 0
62 #define SDRAM_OFFSET(x) 0x2##x
63 #define CONFIG_SYS_SDRAM_BASE 0x20000000
64 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */
68 #define CONFIG_SPL_STACK_R_ADDR 0x2fe00000
69 #define CONFIG_SPL_BSS_START_ADDR 0x2ff80000
71 #define SDRAM_OFFSET(x) 0x4##x
72 #define CONFIG_SYS_SDRAM_BASE 0x40000000
73 #define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */
74 /* V3s do not have enough memory to place code at 0x4a000000 */
78 #define CONFIG_SPL_STACK_R_ADDR 0x4fe00000
79 #define CONFIG_SPL_BSS_START_ADDR 0x4ff80000
82 #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */
85 * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
87 * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the
88 * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and
89 * the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
90 * A64 and H5 also has SRAM A1 at 0x00010000, but no magic remap register
92 * H6 has SRAM A1 at 0x00020000.
96 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
104 #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
128 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
133 #define CONFIG_MMC_SUNXI_SLOT 0
144 #define CONFIG_BOARD_SIZE_LIMIT 0x7e000
152 #define CONFIG_SYS_MMC_ENV_DEV 0
186 #if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000
187 #define CONFIG_SPL_TEXT_BASE 0x10060 /* sram start+header */
188 #define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */
191 #define LOW_LEVEL_SRAM_STACK 0x00054000
193 #define LOW_LEVEL_SRAM_STACK 0x00018000
195 #elif CONFIG_SUNXI_SRAM_ADDRESS == 0x20000
196 #define CONFIG_SPL_TEXT_BASE 0x20060 /* sram start+header */
197 #define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */
199 #define LOW_LEVEL_SRAM_STACK 0x00118000
201 #define CONFIG_SPL_TEXT_BASE 0x60 /* sram start+header */
202 #define CONFIG_SPL_MAX_SIZE 0x5fa0 /* 24KB on sun4i/sun7i */
203 #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */
223 #define CONFIG_SYS_I2C_SLAVE 0x7f
230 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x00
238 #define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */
241 #define CONFIG_SYS_SPD_BUS_NUM 0 /* The axp209 i2c bus is bus 0 */
316 #define BOOTM_SIZE __stringify(0xa000000)
330 #define BOOTM_SIZE __stringify(0xa000000)
342 #define BOOTM_SIZE __stringify(0x2e00000)
352 "bootm_size=" BOOTM_SIZE "\0" \
353 "kernel_addr_r=" KERNEL_ADDR_R "\0" \
354 "fdt_addr_r=" FDT_ADDR_R "\0" \
355 "scriptaddr=" SCRIPT_ADDR_R "\0" \
356 "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \
357 "ramdisk_addr_r=" RAMDISK_ADDR_R "\0"
361 "kernel ram " KERNEL_ADDR_R " 0x1000000;" \
362 "fdt ram " FDT_ADDR_R " 0x100000;" \
363 "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0"
368 BOOTENV_DEV_MMC(MMC, mmc, 0) \
374 "elif test ${mmc_bootdev} -eq 0; then " \
377 "fi\0"
384 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
391 #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0)
397 #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0)
408 "fi\0"
424 "if ext2load mmc 0 0x44000000 uEnv.txt; then " \
426 "env import -t 0x44000000 ${filesize}; " \
429 "ext2load mmc 0 0x43000000 script.bin && " \
430 "ext2load mmc 0 0x48000000 uImage && " \
431 "bootm 0x48000000\0"
440 "preboot=usb start\0" \
441 "stdin=serial,usbkbd\0"
444 "stdin=serial\0"
449 "stdout=serial,vga\0" \
450 "stderr=serial,vga\0"
454 "stdout=serial,vidconsole\0" \
455 "stderr=serial,vidconsole\0"
458 "stdout=serial\0" \
459 "stderr=serial\0"
464 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0"
471 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"
504 "fdtfile=" FDTFILE "\0" \
505 "console=ttyS0,115200\0" \
508 "uuid_gpt_esp=" UUID_GPT_ESP "\0" \
509 "uuid_gpt_system=" UUID_GPT_SYSTEM "\0" \
510 "partitions=" PARTS_DEFAULT "\0" \