Lines Matching +full:0 +full:x7f
77 SICRH_TSOBI2_V2P5) /* 0x0037f103 */
83 SICRL_ETSEC1_TX_CLK) /* 0x00000000 */
88 #define CONFIG_SYS_IMMR 0xE0000000
94 #define CONFIG_FSL_SERDES1 0xe3000
106 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
115 /* 0x7b880001 */
123 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
129 /* 0x80010102 */
130 #define CONFIG_SYS_DDR_TIMING_3 0
131 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
132 | (0 << TIMING_CFG0_WRT_SHIFT) \
133 | (0 << TIMING_CFG0_RRT_SHIFT) \
134 | (0 << TIMING_CFG0_WWT_SHIFT) \
139 /* 0x00260802 */
148 /* 0x26279222 */
149 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
156 /* 0x021848c5 */
157 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
158 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
159 /* 0x08240100 */
163 /* 0x43100000 */
165 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
166 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
167 | (0x0242 << SDRAM_MODE_SD_SHIFT))
168 /* ODT 150ohm CL=4, AL=0 on SDRAM */
169 #define CONFIG_SYS_DDR_MODE2 0x00000000
174 #define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
175 #define CONFIG_SYS_MEMTEST_END 0x07f00000
189 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
190 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
199 #define CONFIG_SYS_LBC_LBCR 0x00040000
208 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
237 #define CONFIG_SYS_FPGA0_BASE 0xE0600000
257 #define CONFIG_SYS_FPGA_DONE(k) 0x0010
273 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
278 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
279 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
287 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
288 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
291 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
292 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
299 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
302 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
305 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
308 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
314 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
317 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
320 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
323 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
332 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
335 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
338 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
341 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
345 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
348 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
351 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
354 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
359 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
362 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
365 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
368 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
376 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
377 {12, 0x4c} }
383 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
384 {12, 0x4c} }
389 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \
390 {8, 0x4c} }
395 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
396 {4, 0x18} }
408 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
409 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
413 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
414 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
417 #define I2C_SDA_GPIO 0x0040
418 #define I2C_SCL_GPIO 0x0020
426 fpga_control_set(I2C_FPGA_IDX, 0x0004); \
428 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
429 } while (0)
436 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
443 } while (0)
450 } while (0)
464 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
474 #define CONFIG_SYS_PCIE1_BASE 0xA0000000
475 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
476 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
477 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
478 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
479 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
480 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
481 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
482 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
490 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
496 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
505 #define TSEC1_PHYIDX 0
506 #define TSEC1_FLAGS 0
508 /* Options are: eTSEC[0-1] */
517 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
518 #define CONFIG_ENV_SIZE 0x2000
522 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
535 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
552 #define CONFIG_SYS_HID0_INIT 0x000000000
615 "netdev=eth0\0" \
616 "consoledev=ttyS1\0" \
617 "u-boot=u-boot.bin\0" \
618 "kernel_addr=1000000\0" \
619 "fdt_addr=C00000\0" \
620 "fdtfile=hrcon.dtb\0" \
621 "load=tftp ${loadaddr} ${u-boot}\0" \
625 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
626 "upd=run load update\0" \
640 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
641 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \