Lines Matching +full:0 +full:x30000000
20 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
29 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
30 #define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
31 #define CONFIG_ENV_SECT_SIZE 0x40000
44 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
45 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
47 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
57 #define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
59 * DDR controller use 0 as the base address for binding.
62 #define CONFIG_SYS_DP_DDR_BASE_PHY 0
70 * will be udpated later when get_bus_freq(0) is available.
91 * During booting, IFC is mapped at the region of 0x30000000.
94 * 0x30000000 - 0x37ffffff : 128MB : NOR flash
95 * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
96 * 0x3C000000 - 0x40000000 : 64MB : FPGA etc
100 * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
101 * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
102 * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
103 * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
104 * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
106 * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
110 * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
113 #define CONFIG_SYS_FLASH_BASE 0x580000000ULL
114 #define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
115 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
117 #define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
118 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
124 #define QIXIS_BASE_PHYS 0x20000000
125 #define QIXIS_BASE_PHYS_EARLY 0xC000000
126 #define QIXIS_STAT_PRES1 0xb
127 #define QIXIS_SDID_MASK 0x07
128 #define QIXIS_ESDHC_NO_ADAPTER 0x7
130 #define CONFIG_SYS_NAND_BASE 0x530000000ULL
131 #define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
135 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
136 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
137 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
138 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
140 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
141 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
161 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
175 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
176 "loadaddr=0x80100000\0" \
177 "kernel_addr=0x100000\0" \
178 "ramdisk_addr=0x800000\0" \
179 "ramdisk_size=0x2000000\0" \
180 "fdt_high=0xa0000000\0" \
181 "initrd_high=0xffffffffffffffff\0" \
182 "kernel_start=0x581000000\0" \
183 "kernel_load=0xa0000000\0" \
184 "kernel_size=0x2800000\0" \
185 "console=ttyAMA0,38400n8\0" \
186 "mcinitcmd=fsl_mc start mc 0x580a00000" \
187 " 0x580e00000 \0"
191 #define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\
192 " fsl_mc apply dpl 0x80200000 &&" \
196 #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
206 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
207 #define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
208 #define CONFIG_SPL_MAX_SIZE 0x16000
209 #define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
211 #define CONFIG_SPL_TEXT_BASE 0x1800a000
214 #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000
217 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
218 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000