Lines Matching +full:0 +full:xfb000000
10 #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
42 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */
43 #define CONFIG_ENV_SIZE 0x004000 /* 16K env */
44 #define CONFIG_ENV_SECT_SIZE 0x010000
45 #define CONFIG_ENV_OFFSET_REDUND 0x110000
46 #define CONFIG_ENV_TOTAL_SIZE 0x020000
53 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
74 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
79 #define CONFIG_SYS_DCSRBAR 0xf0000000
80 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
86 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
94 #define CONFIG_SYS_SPD_BUS_NUM 0
95 #define SPD_EEPROM_ADDRESS 0x54
98 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
115 #define CONFIG_KM_ROOTFSSIZE 0x0
117 #define CONFIG_KM_PNVRAM 0x80000
119 #define CONFIG_KM_PHRAM 0x100000
122 #define CONFIG_KM_RESERVED_PRAM 0x1000
127 #define CONFIG_KM_CRAMFS_ADDR 0x2000000
128 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
129 #define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */
140 #define CONFIG_SYS_NAND_BASE 0xffa00000
141 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
164 #define CONFIG_SYS_QRIO_BASE 0xfb000000
165 #define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull
190 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
191 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
197 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
213 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
215 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
216 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
217 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
218 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
233 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
234 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
235 #define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \
236 {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
237 {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
254 * Memory space is mapped 1-1, but I/O space must start from 0.
258 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
259 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
260 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
261 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
262 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
263 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
264 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
265 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
268 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
269 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
270 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
271 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
272 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000
273 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
274 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull
275 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
279 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
280 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
281 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
282 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
283 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
289 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
291 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
292 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
293 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
294 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
295 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
301 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
306 * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
307 * ucode is stored after env, so we got 0x120000.
310 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000
311 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
312 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
322 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11
367 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
375 "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
378 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
379 "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
380 "u-boot="CONFIG_HOSTNAME "/u-boot.pbl\0" \
382 "sf probe 0;sf erase 0 +${filesize};" \
383 "sf write ${load_addr_r} 0 ${filesize};\0" \
384 "set_fdthigh=true\0" \
385 "checkfdt=true\0" \
389 "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \
390 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
391 "usb_dr_mode=host\0"
394 "newenv=sf probe 0;" \
396 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
400 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
408 "EEprom_ivm=pca9547:70:9\0" \