Lines Matching +full:0 +full:xec800000
27 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
80 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
86 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
89 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
92 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
117 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
118 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
120 #define CONFIG_SYS_CCSRBAR 0xffe00000
140 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
146 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
147 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
148 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
149 #define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
150 #define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
151 #define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
153 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
154 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
155 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
156 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
158 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
159 #define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
160 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
161 #define CONFIG_SYS_DDR_RCW_1 0x00000000
162 #define CONFIG_SYS_DDR_RCW_2 0x00000000
164 #define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
166 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
168 #define CONFIG_SYS_DDR_CONTROL_2 0x04401050
169 #define CONFIG_SYS_DDR_TIMING_4 0x00220001
170 #define CONFIG_SYS_DDR_TIMING_5 0x03402400
172 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
173 #define CONFIG_SYS_DDR_TIMING_0 0x00330004
174 #define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
175 #define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
176 #define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
177 #define CONFIG_SYS_DDR_MODE_1 0x40461520
178 #define CONFIG_SYS_DDR_MODE_2 0x8000c000
179 #define CONFIG_SYS_DDR_INTERVAL 0x0C300000
186 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
187 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
188 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
189 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
191 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
192 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
193 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
200 #define CONFIG_SYS_FLASH_BASE 0xec000000
207 #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
222 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
225 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
228 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
237 #define CONFIG_SYS_PMC_BASE 0xff980000
259 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
267 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
268 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
274 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
275 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
277 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
278 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
279 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
284 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
285 #define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
286 #define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
287 #define CONFIG_SYS_I2C_IDT6V49205B 0x69
292 * Memory space is mapped 1-1, but I/O space must start from 0.
297 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
298 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
299 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
300 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
301 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
302 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
303 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
304 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
308 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
309 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
310 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
311 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
312 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
313 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
314 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
315 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
325 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
326 #define CONFIG_ENV_SIZE 0x20000
327 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
334 #define CONFIG_ENV_SIZE 0x3000 /* 12KB */
335 #define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
336 #define CONFIG_ENV_SECT_SIZE 0x1000
346 #define CONFIG_ENV_SIZE 0x2000
347 #define CONFIG_SYS_MMC_ENV_DEV 0
350 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
351 #define CONFIG_ENV_SIZE 0x2000
355 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
357 #define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
398 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
432 #define TSEC2_PHY_ADDR 0
433 #define TSEC2_PHY_ADDR_SGMII 0x00
440 #define TSEC1_PHYIDX 0
441 #define TSEC2_PHYIDX 0
442 #define TSEC3_PHYIDX 0
457 "bootcmd=run prog_spi_mbrbootcramfs\0" \
458 "bootfile=uImage\0" \
459 "consoledev=ttyS0\0" \
460 "cramfsfile=image.cramfs\0" \
461 "dtbaddr=0x00c00000\0" \
462 "dtbfile=image.dtb\0" \
463 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
464 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
465 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
466 "fileaddr=0x01000000\0" \
467 "filesize=0x00080000\0" \
468 "flashmbr=sf probe 0; " \
471 "sf write $loadaddr $mbr_offset $filesize\0" \
476 "protect on $nor_recoveryaddr +$filesize\0 " \
481 "protect on $nor_ubootaddr +$filesize\0 " \
486 "protect on $nor_workingaddr +$filesize\0 " \
487 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
488 "kerneladdr=0x01100000\0" \
489 "kernelfile=uImage\0" \
490 "loadaddr=0x01000000\0" \
491 "mbr=uCP1020d.mbr\0" \
492 "mbr_offset=0x00000000\0" \
493 "mmbr=uCP1020Quiet.mbr\0" \
494 "mmcpart=0:2\0" \
497 "mmc write $loadaddr 1 1\0" \
499 "mmc erase 0x40 0x400; " \
500 "mmc write $loadaddr 0x40 0x400\0" \
501 "netdev=eth0\0" \
502 "nor_recoveryaddr=0xEC0A0000\0" \
503 "nor_ubootaddr=0xEFF80000\0" \
504 "nor_workingaddr=0xECFA0000\0" \
508 "bootm $kerneladdr - $dtbaddr\0" \
512 "bootm $kerneladdr - $dtbaddr\0" \
513 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
516 "cramfsload $kerneladdr $kernelfile\0" \
517 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
520 "cramfsload $kerneladdr $kernelfile\0" \
521 "prog_spi_mbr=run spi__mbr\0" \
522 "prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
524 "run spi__cramfs\0" \
530 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
531 "ramdisk_size=120000\0" \
532 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
533 "recoveryaddr=0x02F00000\0" \
534 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
535 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
536 "mw.l 0xffe0f008 0x00400000\0" \
537 "rootfsaddr=0x02F00000\0" \
538 "rootfsfile=rootfs.ext2.gz.uboot\0" \
539 "rootpath=/opt/nfsroot\0" \
541 "protect off 0xeC000000 +$filesize; " \
542 "erase 0xEC000000 +$filesize; " \
543 "cp.b $loadaddr 0xEC000000 $filesize; " \
544 "cmp.b $loadaddr 0xEC000000 $filesize; " \
545 "protect on 0xeC000000 +$filesize\0" \
547 "protect off 0xeFF80000 +$filesize; " \
548 "erase 0xEFF80000 +$filesize; " \
549 "cp.b $loadaddr 0xEFF80000 $filesize; " \
550 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
551 "protect on 0xeFF80000 +$filesize\0" \
553 "sf probe 0; sf erase 0x8000 +$filesize; " \
554 "sf write $loadaddr 0x8000 $filesize\0" \
556 "protect off 0xec0a0000 +$filesize; " \
557 "erase 0xeC0A0000 +$filesize; " \
558 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
559 "protect on 0xec0a0000 +$filesize\0" \
561 "sf probe 1; sf erase 0 +$filesize; " \
562 "sf write $loadaddr 0 $filesize\0" \
564 "sf probe 0; sf erase 0 +$filesize; " \
565 "sf write $loadaddr 0 $filesize\0" \
571 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
572 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
573 "ubootaddr=0x01000000\0" \
574 "ubootfile=u-boot.bin\0" \
575 "ubootd=u-boot4dongle.bin\0" \
576 "upgrade=run flashworking\0" \
577 "usb_phy_type=ulpi\0 " \
578 "workingaddr=0x02F00000\0" \
579 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
586 "bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
587 "bootfile=uImage\0" \
588 "consoledev=ttyS0\0" \
589 "cramfsfile=image.cramfs\0" \
590 "dtbaddr=0x00c00000\0" \
591 "dtbfile=image.dtb\0" \
592 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
593 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
594 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
595 "fileaddr=0x01000000\0" \
596 "filesize=0x00080000\0" \
597 "flashmbr=sf probe 0; " \
600 "sf write $loadaddr $mbr_offset $filesize\0" \
605 "protect on $nor_recoveryaddr +$filesize\0 " \
610 "protect on $nor_ubootaddr +$filesize\0 " \
615 "protect on $nor_workingaddr +$filesize\0 " \
616 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
617 "kerneladdr=0x01100000\0" \
618 "kernelfile=uImage\0" \
619 "loadaddr=0x01000000\0" \
620 "mbr=uCP1020.mbr\0" \
621 "mbr_offset=0x00000000\0" \
622 "netdev=eth0\0" \
623 "nor_recoveryaddr=0xEC0A0000\0" \
624 "nor_ubootaddr=0xEFF80000\0" \
625 "nor_workingaddr=0xECFA0000\0" \
629 "bootm $kerneladdr - $dtbaddr\0" \
633 "bootm $kerneladdr - $dtbaddr\0" \
634 "norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
637 "cramfsload $kerneladdr $kernelfile\0" \
638 "norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
641 "cramfsload $kerneladdr $kernelfile\0" \
642 "othbootargs=quiet\0" \
648 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
649 "ramdisk_size=120000\0" \
650 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
651 "recoveryaddr=0x02F00000\0" \
652 "recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
653 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
654 "mw.l 0xffe0f008 0x00400000\0" \
655 "rootfsaddr=0x02F00000\0" \
656 "rootfsfile=rootfs.ext2.gz.uboot\0" \
657 "rootpath=/opt/nfsroot\0" \
658 "silent=1\0" \
664 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
665 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
666 "ubootaddr=0x01000000\0" \
667 "ubootfile=u-boot.bin\0" \
668 "upgrade=run flashworking\0" \
669 "workingaddr=0x02F00000\0" \
670 "workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
675 "bootcmd=run norkernel\0" \
676 "bootfile=uImage\0" \
677 "consoledev=ttyS0\0" \
678 "dtbaddr=0x00c00000\0" \
679 "dtbfile=image.dtb\0" \
680 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
681 "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
682 "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
683 "fileaddr=0x01000000\0" \
684 "filesize=0x00080000\0" \
685 "flashmbr=sf probe 0; " \
688 "sf write $loadaddr $mbr_offset $filesize\0" \
697 "protect on $nor_ubootaddr1 +$filesize\0 " \
699 "erase $part0base +$part0size\0" \
701 "erase $part1base +$part1size\0" \
703 "erase $part2base +$part2size\0" \
705 "erase $part3base +$part3size\0" \
706 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
707 "kerneladdr=0x01100000\0" \
708 "kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
709 "kernelfile=uImage\0" \
710 "loadaddr=0x01000000\0" \
711 "mbr=uCP1020.mbr\0" \
712 "mbr_offset=0x00000000\0" \
713 "netdev=eth0\0" \
714 "nor_ubootaddr0=0xEC000000\0" \
715 "nor_ubootaddr1=0xEFF80000\0" \
718 "bootm $kerneladdr - $dtbaddr\0" \
719 "norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
722 "cramfsload $kerneladdr $kernelfile\0" \
723 "part0base=0xEC100000\0" \
724 "part0size=0x00700000\0" \
725 "part1base=0xEC800000\0" \
726 "part1size=0x02000000\0" \
727 "part2base=0xEE800000\0" \
728 "part2size=0x00800000\0" \
729 "part3base=0xEF000000\0" \
730 "part3size=0x00F80000\0" \
731 "partENVbase=0xEC080000\0" \
732 "partENVsize=0x00080000\0" \
738 "cmp.b $loadaddr $part0base $filesize\0" \
744 "cmp.b $loadaddr $part1base $filesize\0" \
750 "cmp.b $loadaddr $part2base $filesize\0" \
756 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
757 "ramdisk_size=120000\0" \
758 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
759 "releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
760 "mw.l 0xffe0f008 0x00400000\0" \
761 "rootfsaddr=0x02F00000\0" \
762 "rootfsfile=rootfs.ext2.gz.uboot\0" \
763 "rootpath=/opt/nfsroot\0" \
765 "sf probe 0; sf erase 0 +$filesize; " \
766 "sf write $loadaddr 0 $filesize\0" \
768 "protect off 0xeC000000 +$filesize; " \
769 "erase 0xEC000000 +$filesize; " \
770 "cp.b $loadaddr 0xEC000000 $filesize; " \
771 "cmp.b $loadaddr 0xEC000000 $filesize; " \
772 "protect on 0xeC000000 +$filesize\0" \
778 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
779 "uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
780 "ubootfile=u-boot.bin\0" \
781 "upgrade=run flashuboot\0" \
782 "usb_phy_type=ulpi\0 " \
790 "bootm $loadaddr - $fdtaddr\0" \
795 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
796 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
797 "bootm $loadaddr - $fdtaddr\0" \
803 "fatload usb 0:2 $loadaddr $bootfile;" \
804 "fatload usb 0:2 $fdtaddr $fdtfile;" \
805 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
806 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
812 "ext2load usb 0:4 $loadaddr $bootfile;" \
813 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
814 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
815 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
819 "bootm $norbootaddr - $norfdtaddr\0 " \
827 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"