Lines Matching +full:0 +full:x30000000
35 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000
36 #define CONFIG_SPL_PAD_TO 0x40000
37 #define CONFIG_SPL_MAX_SIZE 0x28000
38 #define RESET_VECTOR_OFFSET 0x27FFC
39 #define BOOT_PAGE_OFFSET 0x27000
48 #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
49 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
61 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
64 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
65 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
80 #define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
82 #define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
83 #define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
100 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
109 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
110 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
112 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
113 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
115 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
116 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
123 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
124 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
126 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
127 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
129 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
131 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
132 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
136 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
138 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
140 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
142 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
143 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
147 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
148 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
150 #define CONFIG_ENV_SECT_SIZE 0x10000
152 #define CONFIG_ENV_SECT_SIZE 0x40000
155 #define CONFIG_SYS_MMC_ENV_DEV 0
156 #define CONFIG_ENV_SIZE 0x2000
157 #define CONFIG_ENV_OFFSET (512 * 0x800)
159 #define CONFIG_ENV_SIZE 0x2000
166 #define CONFIG_ENV_ADDR 0xffe20000
167 #define CONFIG_ENV_SIZE 0x2000
169 #define CONFIG_ENV_SIZE 0x2000
172 #define CONFIG_ENV_SIZE 0x2000
173 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
194 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
197 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
198 #define CONFIG_SYS_MEMTEST_END 0x00400000
203 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
214 #define CONFIG_SYS_DCSRBAR 0xf0000000
215 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
221 #define CONFIG_SYS_EEPROM_BUS_NUM 0
222 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
231 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
237 #define CONFIG_SYS_SPD_BUS_NUM 0
238 #define SPD_EEPROM_ADDRESS 0x51
248 #define CONFIG_SYS_FLASH_BASE 0xe8000000
250 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
255 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
266 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
269 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
270 FTIM0_NOR_TEADC(0x5) | \
271 FTIM0_NOR_TEAHC(0x5))
272 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
273 FTIM1_NOR_TRAD_NOR(0x1A) |\
274 FTIM1_NOR_TSEQRAD_NOR(0x13))
275 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
276 FTIM2_NOR_TCH(0x4) | \
277 FTIM2_NOR_TWPH(0x0E) | \
278 FTIM2_NOR_TWP(0x1c))
279 #define CONFIG_SYS_NOR_FTIM3 0x0
294 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
295 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
296 #define CONFIG_SYS_CSPR2_EXT (0xf)
302 #define CONFIG_SYS_CSOR2 0x0
305 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
306 FTIM0_GPCM_TEADC(0x0e) | \
307 FTIM0_GPCM_TEAHC(0x0e))
308 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
309 FTIM1_GPCM_TRAD(0x1f))
310 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
311 FTIM2_GPCM_TCH(0x8) | \
312 FTIM2_GPCM_TWP(0x1f))
313 #define CONFIG_SYS_CS2_FTIM3 0x0
318 #define CONFIG_SYS_NAND_BASE 0xff800000
320 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
324 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
353 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
354 FTIM0_NAND_TWP(0x18) | \
355 FTIM0_NAND_TWCHT(0x07) | \
356 FTIM0_NAND_TWH(0x0a))
357 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
358 FTIM1_NAND_TWBE(0x39) | \
359 FTIM1_NAND_TRR(0x0e) | \
360 FTIM1_NAND_TRP(0x18))
361 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
362 FTIM2_NAND_TREH(0x0a) | \
363 FTIM2_NAND_TWHRE(0x1e))
364 #define CONFIG_SYS_NAND_FTIM3 0x0
421 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
423 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
424 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
430 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
431 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
434 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
446 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
451 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
452 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
453 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
454 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
459 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
474 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
476 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
477 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
478 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
481 #define I2C_PCA6408_ADDR 0x20
484 #define I2C_MUX_CH_DEFAULT 0x8
491 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
499 * Memory space is mapped 1-1, but I/O space must start from 0.
514 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
516 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
517 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
519 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
520 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
522 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
523 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
524 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
526 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
528 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
530 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
535 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
537 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
538 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
540 #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
541 #define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
543 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
544 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
545 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
547 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
549 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
551 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
556 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
558 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
559 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
561 #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
562 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
564 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
565 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
566 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
568 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
570 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
572 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
577 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
579 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
580 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
582 #define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000
583 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000
585 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
586 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
587 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
589 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
591 #define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000
593 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
619 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
621 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
625 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
626 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
627 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
633 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
635 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
637 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
641 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
642 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
643 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
649 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
659 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
660 * env, so we got 0x110000.
663 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
664 #define CONFIG_SYS_QE_FW_ADDR 0x130000
667 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
669 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
672 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
673 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
692 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
695 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
696 #define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
698 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
699 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
706 #define RGMII_PHY1_ADDR 0x2
707 #define RGMII_PHY2_ADDR 0x6
708 #define SGMII_AQR_PHY_ADDR 0x2
709 #define FM1_10GEC1_PHY_ADDR 0x1
711 #define RGMII_PHY1_ADDR 0x1
712 #define SGMII_RTK_PHY_ADDR 0x3
713 #define SGMII_AQR_PHY_ADDR 0x2
734 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
767 "bank_intlv=" __stringify(BANK_INTLV) "\0" \
768 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
769 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
771 __stringify(CONFIG_BOARDNAME) ".dtb\0" \
772 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
773 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
774 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
775 "netdev=eth0\0" \
781 "cmp.b $loadaddr $ubootaddr $filesize\0" \
782 "consoledev=ttyS0\0" \
783 "ramdiskaddr=2000000\0" \
784 "fdtaddr=1e00000\0" \
785 "bdev=sda3\0"
790 "setenv ramdiskaddr 0x02000000;" \
791 "setenv fdtaddr 0x00c00000;" \
792 "setenv loadaddr 0x1000000;" \