Lines Matching +full:0 +full:x17c00000
19 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
23 * default CCSRBAR is at 0xff700000
35 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
57 #define L2_INIT 0
64 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
67 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
68 #define CONFIG_SYS_MEMTEST_END 0x00400000
73 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
76 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
78 #define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
85 #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
104 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
106 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
108 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
117 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
118 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
119 #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
120 #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
126 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
127 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
128 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
129 #define CONFIG_SYS_DDR_TIMING_0 0x00260802
130 #define CONFIG_SYS_DDR_TIMING_1 0x39357322
131 #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
132 #define CONFIG_SYS_DDR_MODE_1 0x00480432
133 #define CONFIG_SYS_DDR_MODE_2 0x00000000
134 #define CONFIG_SYS_DDR_INTERVAL 0x06090100
135 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
136 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
137 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
138 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
139 #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
140 #define CONFIG_SYS_DDR_CONTROL2 0x04400000
145 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
148 #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
157 | 0x00001001) /* port size 16bit */
158 #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
161 | 0x00001001) /* port size 16bit */
162 #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
165 | 0x00000801) /* port size 8bit */
166 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
173 #define CONFIG_SYS_LBC_BASE 0xffde0000
177 #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
178 #define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
181 #define PIXIS_SIZE 0x00008000 /* 32k */
182 #define PIXIS_ID 0x0 /* Board ID at offset 0 */
183 #define PIXIS_VER 0x1 /* Board version at offset 1 */
184 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
185 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */
186 #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
187 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
188 #define PIXIS_VCTL 0x10 /* VELA Control Register */
189 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
190 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
191 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
192 #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
193 #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
194 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
195 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
196 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
197 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
198 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
211 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
230 #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
232 #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
234 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
245 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
250 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
251 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
259 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
260 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
261 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
266 #define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */
268 #define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000
269 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c
272 #define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000
277 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
285 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
287 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
288 #define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
289 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
293 #define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
298 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
299 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
300 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
305 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
325 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
326 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
387 #define TSEC1_PHY_ADDR 0
391 #define TSEC1_PHYIDX 0
392 #define TSEC2_PHYIDX 0
393 #define TSEC3_PHYIDX 0
394 #define TSEC4_PHYIDX 0
405 #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
406 #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
541 #define CONFIG_SYS_DBAT7L 0x00000000
542 #define CONFIG_SYS_DBAT7U 0x00000000
543 #define CONFIG_SYS_IBAT7L 0x00000000
544 #define CONFIG_SYS_IBAT7U 0x00000000
552 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
554 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
556 #define CONFIG_ENV_SIZE 0x2000
571 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
606 #define CONFIG_LOADADDR 0x10000000
609 "netdev=eth0\0" \
610 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
621 " $filesize\0" \
622 "consoledev=ttyS0\0" \
623 "ramdiskaddr=0x18000000\0" \
624 "ramdiskfile=your.ramdisk.u-boot\0" \
625 "fdtaddr=0x17c00000\0" \
626 "fdtfile=mpc8641_hpcn.dtb\0" \
627 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
628 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \