Lines Matching +full:0 +full:xf9000000
11 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB)
12 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB)
13 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB)
14 0xE000_0000-0xEFFF_FFFF IMMR (1 MB)
15 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB)
16 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB)
17 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only)
18 0xF001_0000-0xF001_FFFF Local bus expansion slot
19 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only)
20 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory
21 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only)
27 I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64
29 I2C1 0x20 PCF8574 I2C Expander 0 U8
30 I2C1 0x21 PCF8574 I2C Expander 0 U10
31 I2C1 0x38 PCF8574A I2C Expander 0 U8
32 I2C1 0x39 PCF8574A I2C Expander 0 U10
33 I2C1 0x51 (DDR) DDR EEPROM 1 U1
34 I2C1 0x68 DS1339 RTC 1 U68
42 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
52 #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
78 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
79 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
81 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
82 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
87 #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */
88 #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */
89 #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */
90 #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */
91 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */
92 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/
93 #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */
102 #define I2C_8574_REVISION 0x03
103 #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */
104 #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */
105 #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */
106 #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/
116 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
118 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
119 #define CONFIG_SYS_ATA_REG_OFFSET 0
120 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
157 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
161 #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */
162 #define CONFIG_SYS_MEMTEST_END 0x2000
181 #define CONFIG_SYS_DDR_TIMING_1 0x26242321
182 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */
189 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
202 {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
212 #define CONFIG_VSC7385_IMAGE 0xFEFFE000
241 #define CONFIG_SYS_VSC7385_BASE 0xF8000000
265 #define CONFIG_SYS_LED_BASE 0xF9000000
283 #define CONFIG_SYS_CF_BASE 0xF0000000
308 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
309 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
327 #define CONFIG_SYS_LBC_LBCR 0x00000000
330 #define CONFIG_SYS_LBC_LSRT 0x32000000
332 #define CONFIG_SYS_LBC_MRTPR 0x20000000
339 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
346 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
347 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
361 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
363 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
367 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
368 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
369 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
370 #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
376 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
380 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
381 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
384 #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
388 #define PCI_ENET0_IOADDR 0x00000000
390 #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */
412 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
413 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
414 #define TSEC1_PHYIDX 0
421 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
424 #define TSEC2_PHYIDX 0
440 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
441 #define CONFIG_ENV_SIZE 0x2000
443 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
444 #define CONFIG_ENV_SIZE 0x2000
462 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
512 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
513 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
514 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
515 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
516 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
517 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
519 #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */
529 #define CONFIG_SYS_HID0_INIT 0x00000000
562 #define CONFIG_SYS_IBAT1L 0
563 #define CONFIG_SYS_IBAT1U 0
564 #define CONFIG_SYS_IBAT2L 0
565 #define CONFIG_SYS_IBAT2U 0
585 #define CONFIG_SYS_IBAT3L 0
586 #define CONFIG_SYS_IBAT3U 0
587 #define CONFIG_SYS_IBAT4L 0
588 #define CONFIG_SYS_IBAT4U 0
591 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
601 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
602 #define CONFIG_SYS_IBAT6L (0xF0000000 \
606 #define CONFIG_SYS_IBAT6U (0xF0000000 \
611 #define CONFIG_SYS_IBAT7L 0
612 #define CONFIG_SYS_IBAT7U 0
656 "console=" __stringify(CONSOLE) "\0" \
657 "netdev=" CONFIG_NETDEV "\0" \
658 "uboot=" CONFIG_UBOOTPATH "\0" \
669 " $filesize\0" \
670 "fdtaddr=780000\0" \
671 "fdtfile=" CONFIG_FDTFILE "\0"