Lines Matching +full:0 +full:x4fc
24 unsigned int rev; /* 0x00 - PCU Revision */
25 unsigned int spinfo; /* 0x04 - Scratch Pad Info */
26 unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */
27 unsigned int soc_id; /* 0x10 - SoC ID */
28 unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */
29 unsigned int soc_apb; /* 0x18 - SoC APB configuration */
30 unsigned int rsvd2; /* 0x1C */
31 unsigned int dcsrcr0; /* 0x20 - Driving Capability
32 and Slew Rate Control 0 */
33 unsigned int dcsrcr1; /* 0x24 - Driving Capability
35 unsigned int dcsrcr2; /* 0x28 - Driving Capability
37 unsigned int rsvd3; /* 0x2C */
38 unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */
39 unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */
40 unsigned int dmaes; /* 0x38 - DMA Engine Selection */
41 unsigned int rsvd4; /* 0x3C */
42 unsigned int oscc; /* 0x40 - OSC Control */
43 unsigned int pwmcd; /* 0x44 - PWM Clock divider */
44 unsigned int socmisc; /* 0x48 - SoC Misc. */
45 unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */
46 unsigned int bsmcr; /* 0x80 - BSM Controrl */
47 unsigned int bsmst; /* 0x84 - BSM Status */
48 unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/
49 unsigned int west; /* 0x8C - Wakeup Event Status */
50 unsigned int rsttiming; /* 0x90 - Reset Timing */
51 unsigned int intr_st; /* 0x94 - PCU Interrupt Status */
52 unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */
53 struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */
54 unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */
55 struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */
56 unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */
57 struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */
58 unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */
59 struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */
60 unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */
61 struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */
62 unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */
63 struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */
64 unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */
65 struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */
66 unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */
67 struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */
68 unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */
69 struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */
70 unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */
71 unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager
72 Scratch Pad Memory 0 */
79 #define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff)
80 #define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff)
85 #define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff)
86 #define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf)
91 #define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf)
92 #define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff)
93 #define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff)
98 #define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0)
141 * Driving Capability and Slew Rate Control Register 0 (rw)
143 #define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0)
144 #define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8)
145 #define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12)
146 #define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16)
147 #define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20)
152 #define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0)
157 #define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0)
158 #define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4)
159 #define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8)
160 #define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12)
161 #define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16)
162 #define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20)
163 #define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24)
164 #define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28)
167 * Multi-function Port Setting Register 0 (rw)
169 #define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0)
174 #define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28)
180 #define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0)
212 #define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0)
215 #define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4)
216 #define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6)
217 #define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8)
222 #define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0)
227 #define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0)
231 #define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4)
232 #define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6)
261 #define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0)
262 #define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4)
263 #define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24)
264 #define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28)
270 #define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0)
271 #define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4)
272 #define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24)
273 #define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28)
278 #define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0)
283 #define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0)
288 #define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0)
289 #define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8)
290 #define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16)
291 #define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24)
296 #define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0)
310 #define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0)
311 #define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16)
312 #define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20)
313 #define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */
318 #define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0)
319 #define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24)
320 #define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28)
326 #define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0)
327 #define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28)
332 #define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0)
333 #define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24)
339 #define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0)
340 #define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8)
341 #define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16)
342 #define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24)
344 #define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0)
345 #define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6)
346 #define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12)
347 #define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18)
350 #define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28)