Lines Matching +full:read +full:- +full:1
2 * FILE SA-1100.h
8 * System StrongARM SA-1100
11 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
13 * StrongARM SA-1100 data sheet version 2.2.
15 * Language-specific definitions are selected by the
33 #include <asm/arch-sa1100/bitfield.h>
36 #define Assembly 1
58 #define StMemBnk1Sp StMemBnkSp /* Static Memory Bank 1 Space */
67 #define DRAMBnk1Sp DRAMBnkSp /* DRAM Bank 1 Space [byte] */
76 #define _StMemBnk1 _StMemBnk (1) /* Static Memory Bank 1 */
85 #define StMemBnk1 (StMemBnk [1]) /* Static Memory Bank 1 */
93 #define _DRAMBnk1 _DRAMBnk (1) /* DRAM Bank 1 */
102 #define DRAMBnk1 (DRAMBnk [1]) /* DRAM Bank 1 */
131 #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
132 #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
133 #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
134 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
136 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
138 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
139 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
141 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
149 #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
150 #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
151 #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
152 #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
168 #define PCMCIA1 /* PCMCIA 1 */ \
170 #define PCMCIA1IO /* PCMCIA 1 I/O */ \
172 #define PCMCIA1Attr /* PCMCIA 1 Attribute */ \
174 #define PCMCIA1Mem /* PCMCIA 1 Memory */ \
185 * Controller (UDC) Control Register (read/write).
187 * Controller (UDC) Address Register (read/write).
190 * (read/write).
193 * (read/write).
195 * Controller (UDC) Control/Status register end-point 0
196 * (read/write).
198 * Controller (UDC) Control/Status register end-point 1
199 * (output, read/write).
201 * Controller (UDC) Control/Status register end-point 2
202 * (input, read/write).
204 * Controller (UDC) Data register end-point 0
205 * (read/write).
207 * Controller (UDC) Write Count register end-point 0
208 * (read).
210 * Controller (UDC) Data Register (read/write).
212 * Controller (UDC) Status Register (read/write).
222 /* reg. end-point 0 */
224 /* reg. end-point 1 (output) */
226 /* reg. end-point 2 (input) */
228 /* end-point 0 */
230 /* reg. end-point 0 */
246 /* reg. end-point 0 */ \
249 /* reg. end-point 1 (output) */ \
252 /* reg. end-point 2 (input) */ \
255 /* end-point 0 */ \
258 /* reg. end-point 0 */ \
267 #define UDCCR_UDA 0x00000002 /* UDC Active (read) */
269 #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */
282 #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
285 /* [1..256 byte] */ \
286 (((Size) - 1) << FShft (UDCOMP_OUTMAXP))
288 #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
291 /* [1..256 byte] */ \
292 (((Size) - 1) << FShft (UDCIMP_INMAXP))
294 #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */
299 #define UDCCS0_SE 0x00000020 /* Setup End (read) */
304 #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */
305 /* Service request (read) */
307 #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */
310 #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */
312 #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */
313 /* Service request (read) */
315 #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */
316 #define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */
326 #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */
338 * Ser1UTCR0 Serial port 1 Universal Asynchronous
340 * (read/write).
341 * Ser1UTCR1 Serial port 1 Universal Asynchronous
342 * Receiver/Transmitter (UART) Control Register 1
343 * (read/write).
344 * Ser1UTCR2 Serial port 1 Universal Asynchronous
346 * (read/write).
347 * Ser1UTCR3 Serial port 1 Universal Asynchronous
349 * (read/write).
350 * Ser1UTDR Serial port 1 Universal Asynchronous
352 * (read/write).
353 * Ser1UTSR0 Serial port 1 Universal Asynchronous
355 * (read/write).
356 * Ser1UTSR1 Serial port 1 Universal Asynchronous
357 * Receiver/Transmitter (UART) Status Register 1 (read).
361 * (read/write).
363 * Receiver/Transmitter (UART) Control Register 1
364 * (read/write).
367 * (read/write).
370 * (read/write).
373 * (read/write).
376 * (read/write).
379 * (read/write).
381 * Receiver/Transmitter (UART) Status Register 1 (read).
385 * (read/write).
387 * Receiver/Transmitter (UART) Control Register 1
388 * (read/write).
391 * (read/write).
394 * (read/write).
397 * (read/write).
400 * (read/write).
402 * Receiver/Transmitter (UART) Status Register 1 (read).
410 #define _UTCR0(Nb) /* UART Control Reg. 0 [1..3] */ \
411 (0x80010000 + ((Nb) - 1)*0x00020000)
412 #define _UTCR1(Nb) /* UART Control Reg. 1 [1..3] */ \
413 (0x80010004 + ((Nb) - 1)*0x00020000)
414 #define _UTCR2(Nb) /* UART Control Reg. 2 [1..3] */ \
415 (0x80010008 + ((Nb) - 1)*0x00020000)
416 #define _UTCR3(Nb) /* UART Control Reg. 3 [1..3] */ \
417 (0x8001000C + ((Nb) - 1)*0x00020000)
419 (0x80010010 + ((Nb) - 1)*0x00020000)
420 #define _UTDR(Nb) /* UART Data Reg. [1..3] */ \
421 (0x80010014 + ((Nb) - 1)*0x00020000)
422 #define _UTSR0(Nb) /* UART Status Reg. 0 [1..3] */ \
423 (0x8001001C + ((Nb) - 1)*0x00020000)
424 #define _UTSR1(Nb) /* UART Status Reg. 1 [1..3] */ \
425 (0x80010020 + ((Nb) - 1)*0x00020000)
427 #define _Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */
428 #define _Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */
429 #define _Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */
430 #define _Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */
431 #define _Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */
432 #define _Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */
433 #define _Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */
436 #define _Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */
442 #define _Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */
445 #define _Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */
450 #define _Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */
454 #define Ser1UTCR0 /* Ser. port 1 UART Control Reg. 0 */ \
456 #define Ser1UTCR1 /* Ser. port 1 UART Control Reg. 1 */ \
458 #define Ser1UTCR2 /* Ser. port 1 UART Control Reg. 2 */ \
460 #define Ser1UTCR3 /* Ser. port 1 UART Control Reg. 3 */ \
462 #define Ser1UTDR /* Ser. port 1 UART Data Reg. */ \
464 #define Ser1UTSR0 /* Ser. port 1 UART Status Reg. 0 */ \
466 #define Ser1UTSR1 /* Ser. port 1 UART Status Reg. 1 */ \
471 #define Ser2UTCR1 /* Ser. port 2 UART Control Reg. 1 */ \
483 #define Ser2UTSR1 /* Ser. port 2 UART Status Reg. 1 */ \
488 #define Ser3UTCR1 /* Ser. port 3 UART Control Reg. 1 */ \
498 #define Ser3UTSR1 /* Ser. port 3 UART Status Reg. 1 */ \
532 #define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */
534 #define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */
535 #define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */
537 #define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */
538 #define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */
540 /* (ser. port 1: GPIO [18], */
543 #define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */
544 #define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */
546 #define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */
547 #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */
551 #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
552 #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
553 /* fua = fxtl/(16*(BRD[11:0] + 1)) */
554 /* Tua = 16*(BRD [11:0] + 1)*Txtl */
556 (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
559 (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
564 (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
567 (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
575 #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
577 #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
579 #define UTCR3_LBM 0x00000020 /* Look-Back Mode */
584 #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */
585 /* (HP-SIR) modulation Enable */
586 #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */
587 #define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */
588 #define UTCR4_LPM 0x00000002 /* Low-Power Mode */
590 #define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */
594 #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */
595 #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */
596 #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
599 #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */
600 /* Service request (read) */
601 #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */
602 /* more Service request (read) */
606 #define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */
608 #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
609 #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */
610 #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
611 #define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */
612 #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */
613 #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */
620 * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC)
621 * Control Register 0 (read/write).
622 * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC)
623 * Control Register 1 (read/write).
624 * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC)
625 * Control Register 2 (read/write).
626 * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC)
627 * Control Register 3 (read/write).
628 * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC)
629 * Control Register 4 (read/write).
630 * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC)
631 * Data Register (read/write).
632 * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC)
633 * Status Register 0 (read/write).
634 * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC)
635 * Status Register 1 (read/write).
643 #define _Ser1SDCR0 0x80020060 /* Ser. port 1 SDLC Control Reg. 0 */
644 #define _Ser1SDCR1 0x80020064 /* Ser. port 1 SDLC Control Reg. 1 */
645 #define _Ser1SDCR2 0x80020068 /* Ser. port 1 SDLC Control Reg. 2 */
646 #define _Ser1SDCR3 0x8002006C /* Ser. port 1 SDLC Control Reg. 3 */
647 #define _Ser1SDCR4 0x80020070 /* Ser. port 1 SDLC Control Reg. 4 */
648 #define _Ser1SDDR 0x80020078 /* Ser. port 1 SDLC Data Reg. */
649 #define _Ser1SDSR0 0x80020080 /* Ser. port 1 SDLC Status Reg. 0 */
650 #define _Ser1SDSR1 0x80020084 /* Ser. port 1 SDLC Status Reg. 1 */
653 #define Ser1SDCR0 /* Ser. port 1 SDLC Control Reg. 0 */ \
655 #define Ser1SDCR1 /* Ser. port 1 SDLC Control Reg. 1 */ \
657 #define Ser1SDCR2 /* Ser. port 1 SDLC Control Reg. 2 */ \
659 #define Ser1SDCR3 /* Ser. port 1 SDLC Control Reg. 3 */ \
661 #define Ser1SDCR4 /* Ser. port 1 SDLC Control Reg. 4 */ \
663 #define Ser1SDDR /* Ser. port 1 SDLC Data Reg. */ \
665 #define Ser1SDSR0 /* Ser. port 1 SDLC Status Reg. 0 */ \
667 #define Ser1SDSR1 /* Ser. port 1 SDLC Status Reg. 1 */ \
673 #define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */
676 #define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */
677 #define SDCR0_LBM 0x00000004 /* Look-Back Mode */
680 #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */
685 #define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */
687 #define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */
688 #define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */
690 #define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */
691 #define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */
697 #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
699 #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
702 #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */
703 #define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */
704 #define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */
709 #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
710 #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
711 /* fsd = fxtl/(16*(BRD[11:0] + 1)) */
712 /* Tsd = 16*(BRD[11:0] + 1)*Txtl */
714 (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
717 (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
722 (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
725 (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
732 #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
733 #define SDDR_CRE 0x00000200 /* receive CRC Error (read) */
734 #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
737 #define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */
738 #define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
740 #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
741 /* Service request (read) */
742 #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */
743 /* more Service request (read) */
745 #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
746 #define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */
747 #define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
748 #define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
750 #define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
751 #define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */
752 #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
756 * High-Speed Serial to Parallel controller (HSSP) control registers
759 * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel
760 * controller (HSSP) Control Register 0 (read/write).
761 * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel
762 * controller (HSSP) Control Register 1 (read/write).
763 * Ser2HSDR Serial port 2 High-Speed Serial to Parallel
764 * controller (HSSP) Data Register (read/write).
765 * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel
766 * controller (HSSP) Status Register 0 (read/write).
767 * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel
768 * controller (HSSP) Status Register 1 (read).
769 * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel
770 * controller (HSSP) Control Register 2 (read/write).
773 * SA-1100.]
777 #define _Ser2HSCR1 0x80040064 /* Ser. port 2 HSSP Control Reg. 1 */
780 #define _Ser2HSSR1 0x80040078 /* Ser. port 2 HSSP Status Reg. 1 */
786 #define Ser2HSCR1 /* Ser. port 2 HSSP Control Reg. 1 */ \
792 #define Ser2HSSR1 /* Ser. port 2 HSSP Status Reg. 1 */ \
800 #define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */
801 #define HSCR0_LBM 0x00000002 /* Look-Back Mode */
802 #define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */
803 #define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */
804 #define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */
807 #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */
809 #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */
817 #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
818 #define HSDR_CRE 0x00000200 /* receive CRC Error (read) */
819 #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
822 #define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */
823 #define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
825 #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
826 /* Service request (read) */
827 #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */
828 /* more Service request (read) */
831 #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
832 #define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */
833 #define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
834 #define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
835 #define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
836 #define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */
837 #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */
842 #define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */
843 /* (non-inverted) */
847 #define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */
848 /* (non-inverted) */
852 * Multi-media Communications Port (MCP) control registers
855 * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP)
856 * Control Register 0 (read/write).
857 * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP)
858 * Data Register 0 (audio, read/write).
859 * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP)
860 * Data Register 1 (telecom, read/write).
861 * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP)
862 * Data Register 2 (CODEC registers, read/write).
863 * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP)
864 * Status Register (read/write).
865 * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP)
866 * Control Register 1 (read/write).
869 * SA-1100.]
881 #define _Ser4MCDR1 0x8006000C /* Ser. port 4 MCP Data Reg. 1 */
886 #define _Ser4MCCR1 0x90060030 /* Ser. port 4 MCP Control Reg. 1 */
894 #define Ser4MCDR1 /* Ser. port 4 MCP Data Reg. 1 */ \
902 #define Ser4MCCR1 /* Ser. port 4 MCP Control Reg. 1 */ \
935 #define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */
939 #define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */
940 #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */
942 #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */
944 #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */
946 #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */
948 #define MCCR0_LBM 0x00800000 /* Look-Back Mode */
949 #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */
950 #define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \
951 (((Div) - 1) << FShft (MCCR0_ECP))
962 #define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */
963 #define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */
964 #define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */
967 #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */
968 /* or less Service request (read) */
969 #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */
970 /* more Service request (read) */
971 #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */
972 /* or less Service request (read) */
973 #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */
974 /* or more Service request (read) */
975 #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */
976 #define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */
977 #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */
978 #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */
980 /* (read) */
982 /* (read) */
984 /* (read) */
986 /* (read) */
988 /* (read) */
989 #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */
990 /* (read) */
991 #define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */
992 #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */
997 #define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */
1006 * Register 0 (read/write).
1008 * Register 1 (read/write).
1010 * (rev. = 8) and higher of the StrongARM SA-1100.]
1012 * Register (read/write).
1014 * Register (read/write).
1023 #define _Ser4SSCR1 0x80070064 /* Ser. port 4 SSP Control Reg. 1 */
1030 #define Ser4SSCR1 /* Ser. port 4 SSP Control Reg. 1 */ \
1038 #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */
1040 (((Size) - 1) << FShft (SSCR0_DSS))
1047 (1 << FShft (SSCR0_FRF))
1051 #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */
1052 /* fss = fxtl/(2*(SCR + 1)) */
1053 /* Tss = 2*(SCR + 1)*Txtl */
1055 (((Div) - 2)/2 << FShft (SSCR0_SCR))
1059 (((Div) - 1)/2 << FShft (SSCR0_SCR))
1063 #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */
1065 #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */
1067 #define SSCR1_LBM 0x00000004 /* Look-Back Mode */
1070 #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */
1072 #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */
1073 /* after frame (SFRM, 1st edge) */
1074 #define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */
1075 /* after frame (SFRM, 1st edge) */
1078 #define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */
1082 #define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */
1083 #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
1084 #define SSSR_BSY 0x00000008 /* SSP BuSY (read) */
1085 #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */
1086 /* Service request (read) */
1087 #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */
1088 /* Service request (read) */
1089 #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */
1097 * (read/write).
1098 * OSMR1 Operating System (OS) timer Match Register 1
1099 * (read/write).
1101 * (read/write).
1103 * (read/write).
1105 * (read/write).
1107 * (read/write).
1108 * OWER Operating System (OS) timer Watch-dog Enable Register
1109 * (read/write).
1111 * (read/write).
1117 #define _OSMR1 _OSMR (1) /* OS timer Match Reg. 1 */
1122 #define _OWER 0x90000018 /* OS timer Watch-dog Enable Reg. */
1129 #define OSMR1 (OSMR [1]) /* OS timer Match Reg. 1 */
1136 #define OWER /* OS timer Watch-dog Enable Reg. */ \
1145 #define OSSR_M1 OSSR_M (1) /* Match detected 1 */
1149 #define OWER_WME 0x00000001 /* Watch-dog Match Enable */
1155 #define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */
1161 * Real-Time Clock (RTC) control registers
1164 * RTAR Real-Time Clock (RTC) Alarm Register (read/write).
1165 * RCNR Real-Time Clock (RTC) CouNt Register (read/write).
1166 * RTTR Real-Time Clock (RTC) Trim Register (read/write).
1167 * RTSR Real-Time Clock (RTC) Status Register (read/write).
1170 * frtx, Trtx Frequency, period of the real-time clock crystal
1172 * frtc, Trtc Frequency, period of the real-time clock counter
1173 * (1 Hz nominal).
1192 #define RTTR_C Fld (16, 0) /* clock divider Count - 1 */
1194 /* frtc = (1023*(C + 1) - D)*frtx/ */
1195 /* (1023*(C + 1)^2) */
1196 /* Trtc = (1023*(C + 1)^2)*Trtx/ */
1197 /* (1023*(C + 1) - D) */
1200 #define RTSR_HZ 0x00000002 /* 1 Hz clock detected */
1202 #define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */
1209 * PMCR Power Manager (PM) Control Register (read/write).
1210 * PSSR Power Manager (PM) Sleep Status Register (read/write).
1211 * PSPR Power Manager (PM) Scratch-Pad Register (read/write).
1212 * PWER Power Manager (PM) Wake-up Enable Register
1213 * (read/write).
1215 * (read/write).
1216 * PPCR Power Manager (PM) Phase-Locked Loop (PLL)
1217 * Configuration Register (read/write).
1218 * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO)
1219 * Sleep state Register (read/write, see GPIO pins).
1220 * POSR Power Manager (PM) Oscillator Status Register (read).
1230 #define _PSPR 0x90020008 /* PM Scratch-Pad Reg. */
1231 #define _PWER 0x9002000C /* PM Wake-up Enable Reg. */
1242 #define PSPR /* PM Scratch-Pad Reg. */ \
1244 #define PWER /* PM Wake-up Enable Reg. */ \
1276 #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */
1277 #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
1278 #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
1279 #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
1280 #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
1281 #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
1282 #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
1283 #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
1284 #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
1285 #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
1286 #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
1287 #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
1288 #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
1289 #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
1290 #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
1291 #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
1292 #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
1293 #define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */
1294 #define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */
1295 #define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */
1296 #define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */
1297 #define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */
1298 #define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */
1299 #define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */
1300 #define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */
1301 #define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */
1302 #define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */
1303 #define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */
1304 #define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */
1305 #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
1307 #define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */
1309 #define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */
1311 #define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */
1312 #define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */
1314 #define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */
1315 #define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */
1395 * (read/write).
1396 * RCSR Reset Controller (RC) Status Register (read/write).
1413 #define RCSR_WDR 0x00000004 /* Watch-Dog Reset */
1414 #define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */
1421 * TUCR Test Unit Control Register (read/write).
1438 #define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */
1449 (1 << FShft (TUCR_TSEL))
1467 * General-Purpose Input/Output (GPIO) control registers
1470 * GPLR General-Purpose Input/Output (GPIO) Pin Level
1471 * Register (read).
1472 * GPDR General-Purpose Input/Output (GPIO) Pin Direction
1473 * Register (read/write).
1474 * GPSR General-Purpose Input/Output (GPIO) Pin output Set
1476 * GPCR General-Purpose Input/Output (GPIO) Pin output Clear
1478 * GRER General-Purpose Input/Output (GPIO) Rising-Edge
1479 * detect Register (read/write).
1480 * GFER General-Purpose Input/Output (GPIO) Falling-Edge
1481 * detect Register (read/write).
1482 * GEDR General-Purpose Input/Output (GPIO) Edge Detect
1483 * status Register (read/write).
1484 * GAFR General-Purpose Input/Output (GPIO) Alternate
1485 * Function Register (read/write).
1495 #define _GRER 0x90040010 /* GPIO Rising-Edge detect Reg. */
1496 #define _GFER 0x90040014 /* GPIO Falling-Edge detect Reg. */
1509 #define GRER /* GPIO Rising-Edge detect Reg. */ \
1511 #define GFER /* GPIO Falling-Edge detect Reg. */ \
1536 #define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */
1565 GPIO_GPIO ((Nb) - 6)
1579 /* ser. port 1: */
1584 #define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */
1597 #define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */
1602 #define GPDR_Out 1 /* Output */
1610 * Pending register (read).
1611 * ICMR Interrupt Controller (IC) Mask Register (read/write).
1612 * ICLR Interrupt Controller (IC) Level Register (read/write).
1614 * (read/write).
1616 * (rev. = 8) and higher of the StrongARM SA-1100.]
1618 * (FIQ) Pending register (read).
1619 * ICPR Interrupt Controller (IC) Pending Register (read).
1621 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
1622 * StrongARM SA-1100, it is active high (non-inverted) in
1651 #define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */
1664 #define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */
1665 #define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */
1673 #define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */
1681 #define IC_OST1 IC_OST (1) /* OS Timer match 1 */
1684 #define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */
1688 #define ICLR_FIQ 1 /* Fast Interrupt reQuest */
1690 #define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */
1692 #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */
1694 #define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */
1703 * Register (read/write).
1705 * (read/write).
1707 * Register (read/write).
1708 * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin
1709 * Direction Register (read/write).
1711 * (read).
1717 #define _PSDR 0x9006000C /* PPC Sleep-mode pin Direction */
1728 #define PSDR /* PPC Sleep-mode pin Direction */ \
1738 #define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */
1749 /* ser. port 1: */
1750 #define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */
1751 #define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */
1765 #define PPDR_Out 1 /* Output */
1767 /* ser. port 1: */
1770 #define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */
1775 #define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */
1778 #define PSDR_Flt 1 /* Floating (input) in sleep mode */
1781 #define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */
1782 #define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */
1789 #define PPFR_PPCEn 1 /* PPC Enabled */
1793 * Dynamic Random-Access Memory (DRAM) control registers
1796 * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM)
1797 * CoNFiGuration register (read/write).
1798 * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM)
1800 * (read/write).
1801 * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM)
1802 * Column Address Strobe (CAS) shift register 1
1803 * (read/write).
1804 * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM)
1806 * (read/write).
1819 #define _MDCAS1 _MDCAS (1) /* DRAM CAS shift reg. 1 */
1829 #define MDCAS1 (MDCAS [1]) /* DRAM CAS shift reg. 1 */
1842 #define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */
1845 #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */
1847 (((Add) - 9) << FShft (MDCNFG_DRAC))
1850 #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */
1851 #define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \
1852 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
1854 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
1855 #define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */
1857 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
1859 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
1871 #define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */
1872 #define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */
1873 #define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */
1875 /* bank 0/1 */
1876 #define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */
1877 #define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */
1879 /* deassertion 0/1 */
1880 #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */
1882 #define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */
1883 #define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */
1884 #define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */
1886 /* bank 0/1 */
1887 #define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */
1888 #define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */
1890 /* deassertion 0/1 */
1891 #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */
1899 * (read/write).
1900 * MSC1 Memory system: Static memory Control register 1
1901 * (read/write).
1910 /* [0..1] */ \
1913 #define _MSC1 _MSC (1) /* Static memory Control reg. 1 */
1919 /* [0..1] */ \
1922 #define MSC1 (MSC [1]) /* Static memory Control reg. 1 */
1936 #define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */
1941 #define MSC_NonBrst /* Non-Burst static memory */ \
1943 #define MSC_SRAM /* 32-bit byte-writable SRAM */ \
1944 (1 << FShft (MSC_RT))
1945 #define MSC_Brst4 /* Burst-of-4 static memory */ \
1947 #define MSC_Brst8 /* Burst-of-8 static memory */ \
1950 #define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */
1951 #define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */
1952 #define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */
1953 /* First access - 1(.5) [Tmem] */
1954 #define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \
1956 ((((Tcpu) - 3)/2) << FShft (MSC_RDF))
1957 #define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \
1958 ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1959 #define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \
1961 ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1963 ((((Tcpu) - 1)/2) << FShft (MSC_RDF))
1964 #define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */
1965 /* Next access - 1 [Tmem] */
1966 #define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \
1968 ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1970 ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1971 #define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \
1973 ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1975 ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1990 * Configuration Register (read/write).
2009 #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \
2012 #define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */
2014 #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */
2016 ((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
2018 ((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
2019 #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */
2022 ((((Tcpu) - 2)/2) << FShft (MECR_BSA))
2024 ((((Tcpu) - 1)/2) << FShft (MECR_BSA))
2025 #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */
2027 ((((Tcpu) - 2)/2) << FShft (MECR_BSM))
2029 ((((Tcpu) - 1)/2) << FShft (MECR_BSM))
2050 #define MDREFR_E0PIN (1 << 16)
2051 #define MDREFR_K0RUN (1 << 17)
2052 #define MDREFR_K0DB2 (1 << 18)
2053 #define MDREFR_E1PIN (1 << 20)
2054 #define MDREFR_K1RUN (1 << 21)
2055 #define MDREFR_K1DB2 (1 << 22)
2056 #define MDREFR_K2RUN (1 << 25)
2057 #define MDREFR_K2DB2 (1 << 26)
2058 #define MDREFR_EAPD (1 << 28)
2059 #define MDREFR_KAPD (1 << 29)
2060 #define MDREFR_SLFRSH (1 << 31)
2068 * channel 0 (read/write).
2070 * Register channel 0 (read/write).
2072 * register A channel 0 (read/write).
2074 * register A channel 0 (read/write).
2076 * register B channel 0 (read/write).
2078 * register B channel 0 (read/write).
2081 * channel 1 (read/write).
2083 * Register channel 1 (read/write).
2085 * register A channel 1 (read/write).
2087 * register A channel 1 (read/write).
2089 * register B channel 1 (read/write).
2091 * register B channel 1 (read/write).
2094 * channel 2 (read/write).
2096 * Register channel 2 (read/write).
2098 * register A channel 2 (read/write).
2100 * register A channel 2 (read/write).
2102 * register B channel 2 (read/write).
2104 * register B channel 2 (read/write).
2107 * channel 3 (read/write).
2109 * Register channel 3 (read/write).
2111 * register A channel 3 (read/write).
2113 * register A channel 3 (read/write).
2115 * register B channel 3 (read/write).
2117 * register B channel 3 (read/write).
2120 * channel 4 (read/write).
2122 * Register channel 4 (read/write).
2124 * register A channel 4 (read/write).
2126 * register A channel 4 (read/write).
2128 * register B channel 4 (read/write).
2130 * register B channel 4 (read/write).
2133 * channel 5 (read/write).
2135 * Register channel 5 (read/write).
2137 * register A channel 5 (read/write).
2139 * register A channel 5 (read/write).
2141 * register B channel 5 (read/write).
2143 * register B channel 5 (read/write).
2157 #define _RdDCSR(Nb) /* Read DMA Control & Status Reg. */ \
2158 /* channel [0..5] (read) */ \
2179 #define _RdDCSR0 _RdDCSR (0) /* Read DMA Control & Status Reg. */
2180 /* channel 0 (read) */
2190 #define _DDAR1 _DDAR (1) /* DMA Device Address Reg. */
2191 /* channel 1 */
2192 #define _SetDCSR1 _SetDCSR (1) /* Set DMA Control & Status Reg. */
2193 /* channel 1 (write) */
2194 #define _ClrDCSR1 _ClrDCSR (1) /* Clear DMA Control & Status Reg. */
2195 /* channel 1 (write) */
2196 #define _RdDCSR1 _RdDCSR (1) /* Read DMA Control & Status Reg. */
2197 /* channel 1 (read) */
2198 #define _DBSA1 _DBSA (1) /* DMA Buffer Start address reg. A */
2199 /* channel 1 */
2200 #define _DBTA1 _DBTA (1) /* DMA Buffer Transfer count */
2201 /* reg. A channel 1 */
2202 #define _DBSB1 _DBSB (1) /* DMA Buffer Start address reg. B */
2203 /* channel 1 */
2204 #define _DBTB1 _DBTB (1) /* DMA Buffer Transfer count */
2205 /* reg. B channel 1 */
2213 #define _RdDCSR2 _RdDCSR (2) /* Read DMA Control & Status Reg. */
2214 /* channel 2 (read) */
2230 #define _RdDCSR3 _RdDCSR (3) /* Read DMA Control & Status Reg. */
2231 /* channel 3 (read) */
2247 #define _RdDCSR4 _RdDCSR (4) /* Read DMA Control & Status Reg. */
2248 /* channel 4 (read) */
2264 #define _RdDCSR5 _RdDCSR (5) /* Read DMA Control & Status Reg. */
2265 /* channel 5 (read) */
2286 #define RdDCSR0 /* Read DMA Control & Status Reg. */ \
2287 /* channel 0 (read) */ \
2303 /* channel 1 */ \
2306 /* channel 1 (write) */ \
2309 /* channel 1 (write) */ \
2311 #define RdDCSR1 /* Read DMA Control & Status Reg. */ \
2312 /* channel 1 (read) */ \
2315 /* channel 1 */ \
2318 /* reg. A channel 1 */ \
2321 /* channel 1 */ \
2324 /* reg. B channel 1 */ \
2336 #define RdDCSR2 /* Read DMA Control & Status Reg. */ \
2337 /* channel 2 (read) */ \
2361 #define RdDCSR3 /* Read DMA Control & Status Reg. */ \
2362 /* channel 3 (read) */ \
2386 #define RdDCSR4 /* Read DMA Control & Status Reg. */ \
2387 /* channel 4 (read) */ \
2411 #define RdDCSR5 /* Read DMA Control & Status Reg. */ \
2412 /* channel 5 (read) */ \
2429 #define DDAR_RW 0x00000001 /* device data Read/Write */
2431 /* (memory -> device) */
2432 #define DDAR_DevRd (DDAR_RW*1) /* Device data Read */
2433 /* (device -> memory) */
2436 #define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */
2438 #define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */
2439 #define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */
2441 #define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */
2442 #define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */
2448 #define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \
2450 #define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \
2452 #define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \
2454 #define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \
2470 #define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \
2473 #define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \
2483 (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
2487 #define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \
2490 #define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \
2493 #define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \
2496 #define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \
2499 #define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \
2505 #define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \
2511 #define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \
2517 #define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \
2523 #define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \
2526 #define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \
2530 #define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \
2537 #define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \
2550 #define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */
2562 * (read/write).
2565 * SA-1100.]
2567 * (read/write).
2568 * [Bit LDD can be only read in versions 1.0 (rev. = 1)
2569 * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
2570 * read and written (cleared) in versions 2.0 (rev. = 8)
2573 * (DMA) Base Address Register channel 1 (read/write).
2575 * (DMA) Current Address Register channel 1 (read).
2577 * (DMA) Base Address Register channel 2 (read/write).
2579 * (DMA) Current Address Register channel 2 (read).
2580 * LCCR1 Liquid Crystal Display (LCD) Control Register 1
2581 * (read/write).
2583 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
2584 * StrongARM SA-1100, it can be written and read in
2587 * (read/write).
2589 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
2590 * StrongARM SA-1100, it can be written and read in
2593 * (read/write).
2595 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
2596 * StrongARM SA-1100, it can be written and read in
2599 * the StrongARM SA-1100.]
2610 #define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \
2613 #define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \
2616 #define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \
2617 /* dummy-Palette Space [byte] */ \
2625 #define LCD_4Bit /* LCD 4-Bit pixel mode */ \
2627 #define LCD_8Bit /* LCD 8-Bit pixel mode */ \
2628 (1 << FShft (LCD_PBS))
2629 #define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \
2633 #define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */
2634 #define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */
2639 #define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */
2646 #define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */
2647 #define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
2653 /* channel 1 */
2655 /* channel 1 */
2660 #define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */
2670 /* channel 1 */ \
2673 /* channel 1 */ \
2681 #define LCCR1 /* LCD Control Reg. 1 */ \
2692 #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
2696 #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
2706 #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
2709 #define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */
2712 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
2714 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
2723 #define LCSR_BAU 0x00000002 /* Base Address Update (read) */
2726 #define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */
2728 #define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */
2730 #define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */
2732 #define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */
2734 #define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */
2736 #define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */
2738 #define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */
2740 #define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */
2743 #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */
2745 (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
2747 /* pulse Width - 2 [Tpix] (L_LCLK) */
2750 (((Tpix) - 2) << FShft (LCCR1_HSW))
2751 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
2752 /* count - 1 [Tpix] */
2753 #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
2754 /* [1..256 Tpix] */ \
2755 (((Tpix) - 1) << FShft (LCCR1_ELW))
2756 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
2757 /* Wait count - 1 [Tpix] */
2758 #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
2759 /* [1..256 Tpix] */ \
2760 (((Tpix) - 1) << FShft (LCCR1_BLW))
2762 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
2763 #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
2764 (((Line) - 1) << FShft (LCCR2_LPP))
2766 /* Width - 1 [Tln] (L_FCLK) */
2768 /* Width [1..64 Tln] */ \
2769 (((Tln) - 1) << FShft (LCCR2_VSW))
2770 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
2772 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
2775 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
2777 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
2781 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
2782 /* [1..255] (L_PCLK) */
2786 (((Div) - 4)/2 << FShft (LCCR3_PCD))
2790 (((Div) - 3)/2 << FShft (LCCR3_PCD))
2793 #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */
2796 (((Div) - 2)/2 << FShft (LCCR3_ACB))
2800 (((Div) - 1)/2 << FShft (LCCR3_ACB))
2809 /* [1..15] */ \
2815 #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
2821 #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
2824 #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
2825 #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
2829 #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */