Lines Matching refs:DP_PADCTL
72 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_dp_disable_tx_pu()
217 reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_power_dplanes()
235 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); in tegra_dc_sor_power_dplanes()
247 reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_set_panel_power()
254 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val); in tegra_dc_sor_set_panel_power()
476 reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum)); in tegra_dc_sor_power_up()
496 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_dc_sor_power_up()
596 DUMP_REG(DP_PADCTL(0)); in dump_sor_reg()
597 DUMP_REG(DP_PADCTL(1)); in dump_sor_reg()
846 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_dc_sor_set_lane_parm()
853 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0); in tegra_dc_sor_set_lane_parm()
856 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0); in tegra_dc_sor_set_lane_parm()
918 tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl); in tegra_dc_sor_power_down_unused_lanes()
949 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_sor_precharge_lanes()
953 tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), in tegra_sor_precharge_lanes()