62 	u32 reg_val = tegra_sor_readl(sor, reg);  in tegra_sor_write_field()  local
63 	reg_val &= ~mask;  in tegra_sor_write_field()
64 	reg_val |= val;  in tegra_sor_write_field()
65 	tegra_sor_writel(sor, reg, reg_val);  in tegra_sor_write_field()
93 	u32 reg_val = 0;  in tegra_dc_sor_poll_register()  local
98 		reg_val = tegra_sor_readl(sor, reg);  in tegra_dc_sor_poll_register()
99 		if (((reg_val & mask) == exp_val))  in tegra_dc_sor_poll_register()
105 	      reg, reg_val, mask, exp_val);  in tegra_dc_sor_poll_register()
113 	u32 reg_val;  in tegra_dc_sor_set_power_state()  local
118 	reg_val = pu_pd ? PWR_NORMAL_STATE_PU :  in tegra_dc_sor_set_power_state()
121 	if (reg_val == orig_val)  in tegra_dc_sor_set_power_state()
124 	reg_val |= PWR_SETTING_NEW_TRIGGER;  in tegra_dc_sor_set_power_state()
125 	tegra_sor_writel(sor, PWR, reg_val);  in tegra_dc_sor_set_power_state()
144 	u32 reg_val;  in tegra_dc_sor_set_dp_linkctl()  local
146 	reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));  in tegra_dc_sor_set_dp_linkctl()
149 		reg_val |= DP_LINKCTL_ENABLE_YES;  in tegra_dc_sor_set_dp_linkctl()
151 		reg_val &= DP_LINKCTL_ENABLE_NO;  in tegra_dc_sor_set_dp_linkctl()
153 	reg_val &= ~DP_LINKCTL_TUSIZE_MASK;  in tegra_dc_sor_set_dp_linkctl()
154 	reg_val |= (link_cfg->tu_size << DP_LINKCTL_TUSIZE_SHIFT);  in tegra_dc_sor_set_dp_linkctl()
157 		reg_val |= DP_LINKCTL_ENHANCEDFRAME_ENABLE;  in tegra_dc_sor_set_dp_linkctl()
159 	tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);  in tegra_dc_sor_set_dp_linkctl()
167 		reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ?  in tegra_dc_sor_set_dp_linkctl()
169 		tegra_sor_writel(sor, DP_TPG, reg_val);  in tegra_dc_sor_set_dp_linkctl()
180 	u32 reg_val;  in tegra_dc_sor_enable_lane_sequencer()  local
184 		reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER |  in tegra_dc_sor_enable_lane_sequencer()
188 		reg_val = LANE_SEQ_CTL_SETTING_NEW_TRIGGER |  in tegra_dc_sor_enable_lane_sequencer()
194 		reg_val |= 15 << LANE_SEQ_CTL_DELAY_SHIFT;  in tegra_dc_sor_enable_lane_sequencer()
196 		reg_val |= 1 << LANE_SEQ_CTL_DELAY_SHIFT;  in tegra_dc_sor_enable_lane_sequencer()
198 	tegra_sor_writel(sor, LANE_SEQ_CTL, reg_val);  in tegra_dc_sor_enable_lane_sequencer()
215 	u32 reg_val;  in tegra_dc_sor_power_dplanes()  local
217 	reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));  in tegra_dc_sor_power_dplanes()
222 			reg_val |= (DP_PADCTL_PD_TXD_3_NO |  in tegra_dc_sor_power_dplanes()
226 			reg_val |= DP_PADCTL_PD_TXD_1_NO;  in tegra_dc_sor_power_dplanes()
228 			reg_val |= DP_PADCTL_PD_TXD_0_NO;  in tegra_dc_sor_power_dplanes()
235 		tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);  in tegra_dc_sor_power_dplanes()
245 	u32 reg_val;  in tegra_dc_sor_set_panel_power()  local
247 	reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));  in tegra_dc_sor_set_panel_power()
250 		reg_val |= DP_PADCTL_PAD_CAL_PD_POWERUP;  in tegra_dc_sor_set_panel_power()
252 		reg_val &= ~DP_PADCTL_PAD_CAL_PD_POWERUP;  in tegra_dc_sor_set_panel_power()
254 	tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);  in tegra_dc_sor_set_panel_power()
277 	u32 reg_val;  in tegra_dc_sor_set_dp_mode()  local
282 	reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum));  in tegra_dc_sor_set_dp_mode()
283 	reg_val &= ~DP_CONFIG_WATERMARK_MASK;  in tegra_dc_sor_set_dp_mode()
284 	reg_val |= link_cfg->watermark;  in tegra_dc_sor_set_dp_mode()
285 	reg_val &= ~DP_CONFIG_ACTIVESYM_COUNT_MASK;  in tegra_dc_sor_set_dp_mode()
286 	reg_val |= (link_cfg->active_count <<  in tegra_dc_sor_set_dp_mode()
288 	reg_val &= ~DP_CONFIG_ACTIVESYM_FRAC_MASK;  in tegra_dc_sor_set_dp_mode()
289 	reg_val |= (link_cfg->active_frac <<  in tegra_dc_sor_set_dp_mode()
292 		reg_val |= DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;  in tegra_dc_sor_set_dp_mode()
294 		reg_val &= ~DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE;  in tegra_dc_sor_set_dp_mode()
295 	reg_val |= (DP_CONFIG_ACTIVESYM_CNTL_ENABLE |  in tegra_dc_sor_set_dp_mode()
298 	tegra_sor_writel(sor, DP_CONFIG(sor->portnum), reg_val);  in tegra_dc_sor_set_dp_mode()
326 	u32 reg_val;  in tegra_dc_sor_io_set_dpd()  local
335 	reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_REQ);  in tegra_dc_sor_io_set_dpd()
336 	reg_val &= ~(APBDEV_PMC_IO_DPD2_REQ_LVDS_ON ||  in tegra_dc_sor_io_set_dpd()
339 	reg_val = up ? APBDEV_PMC_IO_DPD2_REQ_LVDS_ON |  in tegra_dc_sor_io_set_dpd()
344 	writel(reg_val, pmc_base + APBDEV_PMC_IO_DPD2_REQ);  in tegra_dc_sor_io_set_dpd()
350 		reg_val = readl(pmc_base + APBDEV_PMC_IO_DPD2_STATUS);  in tegra_dc_sor_io_set_dpd()
355 	} while ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0);  in tegra_dc_sor_io_set_dpd()
357 	if ((reg_val & APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON) != 0) {  in tegra_dc_sor_io_set_dpd()
358 		debug("PMC_IO_DPD2 polling failed (0x%x)\n", reg_val);  in tegra_dc_sor_io_set_dpd()
373 	u32 reg_val;  in tegra_dc_sor_set_internal_panel()  local
375 	reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum));  in tegra_dc_sor_set_internal_panel()
377 		reg_val |= DP_SPARE_PANEL_INTERNAL;  in tegra_dc_sor_set_internal_panel()
379 		reg_val &= ~DP_SPARE_PANEL_INTERNAL;  in tegra_dc_sor_set_internal_panel()
381 	reg_val |= DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK |  in tegra_dc_sor_set_internal_panel()
383 	tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val);  in tegra_dc_sor_set_internal_panel()
390 	u32 reg_val;  in tegra_dc_sor_read_link_config()  local
392 	reg_val = tegra_sor_readl(sor, CLK_CNTRL);  in tegra_dc_sor_read_link_config()
393 	*link_bw = (reg_val & CLK_CNTRL_DP_LINK_SPEED_MASK)  in tegra_dc_sor_read_link_config()
395 	reg_val = tegra_sor_readl(sor,  in tegra_dc_sor_read_link_config()
398 	switch (reg_val & DP_LINKCTL_LANECOUNT_MASK) {  in tegra_dc_sor_read_link_config()
428 	u32 reg_val;  in tegra_dc_sor_set_lane_count()  local
430 	reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));  in tegra_dc_sor_set_lane_count()
431 	reg_val &= ~DP_LINKCTL_LANECOUNT_MASK;  in tegra_dc_sor_set_lane_count()
436 		reg_val |= DP_LINKCTL_LANECOUNT_ONE;  in tegra_dc_sor_set_lane_count()
439 		reg_val |= DP_LINKCTL_LANECOUNT_TWO;  in tegra_dc_sor_set_lane_count()
442 		reg_val |= DP_LINKCTL_LANECOUNT_FOUR;  in tegra_dc_sor_set_lane_count()
449 	tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);  in tegra_dc_sor_set_lane_count()
614 	u32		reg_val	 = STATE1_ASY_OWNER_HEAD0 << head_num;  in tegra_dc_sor_config_panel()  local
620 	reg_val |= is_lvds ? STATE1_ASY_PROTOCOL_LVDS_CUSTOM :  in tegra_dc_sor_config_panel()
622 	reg_val |= STATE1_ASY_SUBOWNER_NONE |  in tegra_dc_sor_config_panel()
625 	reg_val |= STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE;  in tegra_dc_sor_config_panel()
626 	reg_val |= STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE;  in tegra_dc_sor_config_panel()
627 	reg_val |= (link_cfg->bits_per_pixel > 18) ?  in tegra_dc_sor_config_panel()
631 	tegra_sor_writel(sor, STATE1, reg_val);  in tegra_dc_sor_config_panel()
679 	u32 reg_val = readl(&disp_ctrl->cmd.state_access);  in tegra_dc_sor_enable_dc()  local
681 	writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);  in tegra_dc_sor_enable_dc()
687 	writel(reg_val, &disp_ctrl->cmd.state_access);  in tegra_dc_sor_enable_dc()
761 	u32 reg_val;  in tegra_dc_sor_attach()  local
777 	reg_val = tegra_sor_readl(sor, TEST);  in tegra_dc_sor_attach()
778 	if (reg_val & TEST_ATTACHED_TRUE)  in tegra_dc_sor_attach()
804 	reg_val = readl(&disp_ctrl->cmd.state_access);  in tegra_dc_sor_attach()
805 	writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);  in tegra_dc_sor_attach()
809 	writel(reg_val, &disp_ctrl->cmd.state_access);  in tegra_dc_sor_attach()
962 	u32 reg_val = readl(&disp_ctrl->disp.disp_win_opt);  in tegra_dc_sor_enable_sor()  local
964 	reg_val = enable ? reg_val | SOR_ENABLE : reg_val & ~SOR_ENABLE;  in tegra_dc_sor_enable_sor()
965 	writel(reg_val, &disp_ctrl->disp.disp_win_opt);  in tegra_dc_sor_enable_sor()