1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2011-2013, NVIDIA Corporation.
15 #include <asm/arch-tegra/dc.h>
50 	return readl((u32 *)sor->base + reg);  in tegra_sor_readl()
56 	writel(val, (u32 *)sor->base + reg);  in tegra_sor_writel()
72 	tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),  in tegra_dp_disable_tx_pu()
81 	tegra_sor_write_field(sor, PR(sor->portnum), mask, pe_reg);  in tegra_dp_set_pe_vs_pc()
82 	tegra_sor_write_field(sor, DC(sor->portnum), mask, vs_reg);  in tegra_dp_set_pe_vs_pc()
84 		tegra_sor_write_field(sor, POSTCURSOR(sor->portnum), mask,  in tegra_dp_set_pe_vs_pc()
107 	return -ETIMEDOUT;  in tegra_dc_sor_poll_register()
133 		return -EFAULT;  in tegra_dc_sor_set_power_state()
146 	reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));  in tegra_dc_sor_set_dp_linkctl()
154 	reg_val |= (link_cfg->tu_size << DP_LINKCTL_TUSIZE_SHIFT);  in tegra_dc_sor_set_dp_linkctl()
156 	if (link_cfg->enhanced_framing)  in tegra_dc_sor_set_dp_linkctl()
159 	tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);  in tegra_dc_sor_set_dp_linkctl()
167 		reg_val = (link_cfg->link_bw == SOR_LINK_SPEED_G5_4) ?  in tegra_dc_sor_set_dp_linkctl()
205 		return -1;  in tegra_dc_sor_enable_lane_sequencer()
217 	reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));  in tegra_dc_sor_power_dplanes()
232 			return -1;  in tegra_dc_sor_power_dplanes()
235 		tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);  in tegra_dc_sor_power_dplanes()
247 	reg_val = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));  in tegra_dc_sor_set_panel_power()
254 	tegra_sor_writel(sor, DP_PADCTL(sor->portnum), reg_val);  in tegra_dc_sor_set_panel_power()
279 	tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw);  in tegra_dc_sor_set_dp_mode()
282 	reg_val = tegra_sor_readl(sor, DP_CONFIG(sor->portnum));  in tegra_dc_sor_set_dp_mode()
284 	reg_val |= link_cfg->watermark;  in tegra_dc_sor_set_dp_mode()
286 	reg_val |= (link_cfg->active_count <<  in tegra_dc_sor_set_dp_mode()
289 	reg_val |= (link_cfg->active_frac <<  in tegra_dc_sor_set_dp_mode()
291 	if (link_cfg->activepolarity)  in tegra_dc_sor_set_dp_mode()
298 	tegra_sor_writel(sor, DP_CONFIG(sor->portnum), reg_val);  in tegra_dc_sor_set_dp_mode()
303 			      link_cfg->hblank_sym);  in tegra_dc_sor_set_dp_mode()
307 			      link_cfg->vblank_sym);  in tegra_dc_sor_set_dp_mode()
327 	void *pmc_base = sor->pmc_base;  in tegra_dc_sor_io_set_dpd()
352 			temp -= 20;  in tegra_dc_sor_io_set_dpd()
359 		return -EIO;  in tegra_dc_sor_io_set_dpd()
375 	reg_val = tegra_sor_readl(sor, DP_SPARE(sor->portnum));  in tegra_dc_sor_set_internal_panel()
383 	tegra_sor_writel(sor, DP_SPARE(sor->portnum), reg_val);  in tegra_dc_sor_set_internal_panel()
396 		DP_LINKCTL(sor->portnum));  in tegra_dc_sor_read_link_config()
430 	reg_val = tegra_sor_readl(sor, DP_LINKCTL(sor->portnum));  in tegra_dc_sor_set_lane_count()
449 	tegra_sor_writel(sor, DP_LINKCTL(sor->portnum), reg_val);  in tegra_dc_sor_set_lane_count()
469 	if (sor->power_is_up)  in tegra_dc_sor_power_up()
474 	 * This can happen if U-Boot is the secondary boot loader.  in tegra_dc_sor_power_up()
476 	reg = tegra_sor_readl(sor, DP_PADCTL(sor->portnum));  in tegra_dc_sor_power_up()
496 	tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),  in tegra_dc_sor_power_up()
528 	sor->power_is_up = 1;  in tegra_dc_sor_power_up()
537 		"%-32s  %03x  %08x\n",		\  in dump_sor_reg()
589 	DUMP_REG(PR(0));  in dump_sor_reg()
627 	reg_val |= (link_cfg->bits_per_pixel > 18) ?  in tegra_dc_sor_config_panel()
637 	vtotal = timing->vsync_len.typ + timing->vback_porch.typ +  in tegra_dc_sor_config_panel()
638 		timing->vactive.typ + timing->vfront_porch.typ;  in tegra_dc_sor_config_panel()
639 	htotal = timing->hsync_len.typ + timing->hback_porch.typ +  in tegra_dc_sor_config_panel()
640 		timing->hactive.typ + timing->hfront_porch.typ;  in tegra_dc_sor_config_panel()
646 	vsync_end = timing->vsync_len.typ - 1;  in tegra_dc_sor_config_panel()
647 	hsync_end = timing->hsync_len.typ - 1;  in tegra_dc_sor_config_panel()
652 	vblank_end = vsync_end + timing->vback_porch.typ;  in tegra_dc_sor_config_panel()
653 	hblank_end = hsync_end + timing->hback_porch.typ;  in tegra_dc_sor_config_panel()
658 	vblank_start = vblank_end + timing->vactive.typ;  in tegra_dc_sor_config_panel()
659 	hblank_start = hblank_end + timing->hactive.typ;  in tegra_dc_sor_config_panel()
679 	u32 reg_val = readl(&disp_ctrl->cmd.state_access);  in tegra_dc_sor_enable_dc()
681 	writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);  in tegra_dc_sor_enable_dc()
682 	writel(VSYNC_H_POSITION(1), &disp_ctrl->disp.disp_timing_opt);  in tegra_dc_sor_enable_dc()
684 	/* Enable DC now - otherwise pure text console may not show. */  in tegra_dc_sor_enable_dc()
686 	       &disp_ctrl->cmd.disp_cmd);  in tegra_dc_sor_enable_dc()
687 	writel(reg_val, &disp_ctrl->cmd.state_access);  in tegra_dc_sor_enable_dc()
728 		printf("DP failed to lock PLL\n");  in tegra_dc_sor_enable_dp()
729 		return -EIO;  in tegra_dc_sor_enable_dp()
743 	/* re-enable SOR clock */  in tegra_dc_sor_enable_dp()
747 	tegra_dc_sor_power_dplanes(dev, link_cfg->lane_count, 1);  in tegra_dc_sor_enable_dp()
770 	writel(0x9f00, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_attach()
771 	writel(0x9f, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_attach()
775 	       &disp_ctrl->cmd.disp_pow_ctrl);  in tegra_dc_sor_attach()
779 		return -EEXIST;  in tegra_dc_sor_attach()
788 	writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);  in tegra_dc_sor_attach()
789 	writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_attach()
790 	writel(0, &disp_ctrl->disp.disp_win_opt);  in tegra_dc_sor_attach()
791 	writel(GENERAL_ACT_REQ, &disp_ctrl->cmd.state_ctrl);  in tegra_dc_sor_attach()
804 	reg_val = readl(&disp_ctrl->cmd.state_access);  in tegra_dc_sor_attach()
805 	writel(reg_val | WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access);  in tegra_dc_sor_attach()
807 	       &disp_ctrl->cmd.disp_cmd);  in tegra_dc_sor_attach()
808 	writel(SOR_ENABLE, &disp_ctrl->disp.disp_win_opt);  in tegra_dc_sor_attach()
809 	writel(reg_val, &disp_ctrl->cmd.state_access);  in tegra_dc_sor_attach()
817 		return -ETIMEDOUT;  in tegra_dc_sor_attach()
835 	tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum),  in tegra_dc_sor_set_lane_parm()
836 			 link_cfg->drive_current);  in tegra_dc_sor_set_lane_parm()
837 	tegra_sor_writel(sor, PR(sor->portnum),  in tegra_dc_sor_set_lane_parm()
838 			 link_cfg->preemphasis);  in tegra_dc_sor_set_lane_parm()
839 	tegra_sor_writel(sor, POSTCURSOR(sor->portnum),  in tegra_dc_sor_set_lane_parm()
840 			 link_cfg->postcursor);  in tegra_dc_sor_set_lane_parm()
843 	tegra_dc_sor_set_link_bandwidth(dev, link_cfg->link_bw);  in tegra_dc_sor_set_lane_parm()
844 	tegra_dc_sor_set_lane_count(dev, link_cfg->lane_count);  in tegra_dc_sor_set_lane_parm()
846 	tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),  in tegra_dc_sor_set_lane_parm()
853 	tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0xf0);  in tegra_dc_sor_set_lane_parm()
856 	tegra_sor_write_field(sor, DP_PADCTL(sor->portnum), 0xf0, 0x0);  in tegra_dc_sor_set_lane_parm()
866 	/* Set to a known-good pre-calibrated setting */  in tegra_dc_sor_set_voltage_swing()
867 	switch (link_cfg->link_bw) {  in tegra_dc_sor_set_voltage_swing()
876 		debug("Invalid sor link bandwidth: %d\n", link_cfg->link_bw);  in tegra_dc_sor_set_voltage_swing()
877 		return -ENOLINK;  in tegra_dc_sor_set_voltage_swing()
880 	tegra_sor_writel(sor, LANE_DRIVE_CURRENT(sor->portnum), drive_current);  in tegra_dc_sor_set_voltage_swing()
881 	tegra_sor_writel(sor, PR(sor->portnum), pre_emphasis);  in tegra_dc_sor_set_voltage_swing()
893 	switch (link_cfg->lane_count) {  in tegra_dc_sor_power_down_unused_lanes()
913 		printf("Invalid sor lane count: %u\n", link_cfg->lane_count);  in tegra_dc_sor_power_down_unused_lanes()
918 	tegra_sor_writel(sor, DP_PADCTL(sor->portnum), pad_ctrl);  in tegra_dc_sor_power_down_unused_lanes()
933 	switch (cfg->lane_count) {  in tegra_sor_precharge_lanes()
945 		debug("dp: invalid lane number %d\n", cfg->lane_count);  in tegra_sor_precharge_lanes()
946 		return -EINVAL;  in tegra_sor_precharge_lanes()
949 	tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),  in tegra_sor_precharge_lanes()
953 	tegra_sor_write_field(sor, DP_PADCTL(sor->portnum),  in tegra_sor_precharge_lanes()
962 	u32 reg_val = readl(&disp_ctrl->disp.disp_win_opt);  in tegra_dc_sor_enable_sor()
965 	writel(reg_val, &disp_ctrl->disp.disp_win_opt);  in tegra_dc_sor_enable_sor()
993 		ret = -ETIMEDOUT;  in tegra_dc_sor_detach()
1002 	dc_int_mask = readl(&disp_ctrl->cmd.int_mask);  in tegra_dc_sor_detach()
1003 	writel(0, &disp_ctrl->cmd.int_mask);  in tegra_dc_sor_detach()
1005 	/* Stop DC->SOR path */  in tegra_dc_sor_detach()
1012 	writel(CTRL_MODE_STOP << CTRL_MODE_SHIFT, &disp_ctrl->cmd.disp_cmd);  in tegra_dc_sor_detach()
1019 	writel(dc_int_mask, &disp_ctrl->cmd.int_mask);  in tegra_dc_sor_detach()
1033 	ret = panel_enable_backlight(priv->panel);  in tegra_sor_set_backlight()
1047 	priv->base = (void *)dev_read_addr(dev);  in tegra_sor_ofdata_to_platdata()
1049 	priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC);  in tegra_sor_ofdata_to_platdata()
1050 	if (IS_ERR(priv->pmc_base))  in tegra_sor_ofdata_to_platdata()
1051 		return PTR_ERR(priv->pmc_base);  in tegra_sor_ofdata_to_platdata()
1054 					   &priv->panel);  in tegra_sor_ofdata_to_platdata()
1057 		      dev->name, ret);  in tegra_sor_ofdata_to_platdata()
1069 	{ .compatible = "nvidia,tegra124-sor" },