Lines Matching defs:reg_val
62 u32 reg_val = tegra_sor_readl(sor, reg); in tegra_sor_write_field() local
93 u32 reg_val = 0; in tegra_dc_sor_poll_register() local
113 u32 reg_val; in tegra_dc_sor_set_power_state() local
144 u32 reg_val; in tegra_dc_sor_set_dp_linkctl() local
180 u32 reg_val; in tegra_dc_sor_enable_lane_sequencer() local
215 u32 reg_val; in tegra_dc_sor_power_dplanes() local
245 u32 reg_val; in tegra_dc_sor_set_panel_power() local
277 u32 reg_val; in tegra_dc_sor_set_dp_mode() local
326 u32 reg_val; in tegra_dc_sor_io_set_dpd() local
373 u32 reg_val; in tegra_dc_sor_set_internal_panel() local
390 u32 reg_val; in tegra_dc_sor_read_link_config() local
428 u32 reg_val; in tegra_dc_sor_set_lane_count() local
614 u32 reg_val = STATE1_ASY_OWNER_HEAD0 << head_num; in tegra_dc_sor_config_panel() local
679 u32 reg_val = readl(&disp_ctrl->cmd.state_access); in tegra_dc_sor_enable_dc() local
761 u32 reg_val; in tegra_dc_sor_attach() local
962 u32 reg_val = readl(&disp_ctrl->disp.disp_win_opt); in tegra_dc_sor_enable_sor() local