Lines Matching refs:tegra_dc_dp_dpcd_write

341 static int tegra_dc_dp_dpcd_write(struct tegra_dp_priv *dp, u32 cmd,  in tegra_dc_dp_dpcd_write()  function
725 	ret = tegra_dc_dp_dpcd_write(priv, DP_EDP_CONFIGURATION_SET,  in tegra_dc_dp_set_assr()
742 	return tegra_dc_dp_dpcd_write(dp, DP_LINK_BW_SET, link_bw);  in tegra_dp_set_link_bandwidth()
756 	ret = tegra_dc_dp_dpcd_write(dp, DP_LANE_COUNT_SET, dpcd_data);  in tegra_dp_set_lane_count()
920 	tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, data);  in tegra_dp_tpg()
945 			ret = tegra_dc_dp_dpcd_write(dp, DP_SET_POWER,  in tegra_dp_link_config()
1065 		tegra_dc_dp_dpcd_write(dp, (DP_TRAINING_LANE0_SET + cnt), val);  in tegra_dp_lt_config()
1081 			tegra_dc_dp_dpcd_write(dp,  in tegra_dp_lt_config()
1247 	tegra_dc_dp_dpcd_write(dp, DP_MAIN_LINK_CHANNEL_CODING_SET,  in tegra_dc_dp_fast_link_training()
1252 	tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET,  in tegra_dc_dp_fast_link_training()
1256 		tegra_dc_dp_dpcd_write(dp, DP_TRAINING_LANE0_SET + j, 0x24);  in tegra_dc_dp_fast_link_training()
1273 	tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET,  in tegra_dc_dp_fast_link_training()
1276 		tegra_dc_dp_dpcd_write(dp, DP_TRAINING_LANE0_SET + j, 0x24);  in tegra_dc_dp_fast_link_training()
1289 	tegra_dc_dp_dpcd_write(dp, DP_TRAINING_PATTERN_SET, 0);  in tegra_dc_dp_fast_link_training()
1511 		ret = tegra_dc_dp_dpcd_write(priv, DP_SET_POWER, data);  in tegra_dp_enable()