Lines Matching full:write
28 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
36 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
39 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
40 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
44 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
48 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
49 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
50 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
52 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
53 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
54 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
55 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
56 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
61 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
66 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
71 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
80 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
87 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
90 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
91 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
94 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
95 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
96 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
97 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
98 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
99 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
100 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
101 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
102 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
103 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
104 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
105 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
106 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
107 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
108 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
109 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
110 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
111 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
112 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
113 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
114 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
115 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
116 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
117 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
118 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
119 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
120 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
121 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
122 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
123 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
124 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
125 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
126 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
127 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
128 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
129 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
130 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
131 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
132 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
133 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
134 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
135 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
143 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
151 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
152 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
157 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
162 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
163 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
170 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
174 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
177 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
181 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
182 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
183 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
184 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
185 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
186 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
187 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
188 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
189 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
196 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
200 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
205 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
206 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
207 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
208 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
209 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
212 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
214 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
220 #define REG_TX3 REG(0x12, 0x9a) /* read/write */
221 #define REG_TX4 REG(0x12, 0x9b) /* read/write */
223 #define REG_TX33 REG(0x12, 0xb8) /* read/write */
227 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
232 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
236 #define TDA19988_CEC_ENAMODS 0xff /* read/write */
590 /* Write the default value MUX register */ in tda19988_probe()