Lines Matching +full:m +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0+
42 * Due to missing documentaion of HDMI PHY, we know correct in sunxi_dw_hdmi_get_divider()
43 * settings only for following four PHY dividers. Select one in sunxi_dw_hdmi_get_divider()
58 struct sunxi_hdmi_phy * const phy = in sunxi_dw_hdmi_phy_init() local
64 * HDMI PHY settings are taken as-is from Allwinner BSP code. in sunxi_dw_hdmi_phy_init()
67 writel(0, &phy->ctrl); in sunxi_dw_hdmi_phy_init()
68 setbits_le32(&phy->ctrl, BIT(0)); in sunxi_dw_hdmi_phy_init()
70 setbits_le32(&phy->ctrl, BIT(16)); in sunxi_dw_hdmi_phy_init()
71 setbits_le32(&phy->ctrl, BIT(1)); in sunxi_dw_hdmi_phy_init()
73 setbits_le32(&phy->ctrl, BIT(2)); in sunxi_dw_hdmi_phy_init()
75 setbits_le32(&phy->ctrl, BIT(3)); in sunxi_dw_hdmi_phy_init()
77 setbits_le32(&phy->ctrl, BIT(19)); in sunxi_dw_hdmi_phy_init()
79 setbits_le32(&phy->ctrl, BIT(18)); in sunxi_dw_hdmi_phy_init()
80 setbits_le32(&phy->ctrl, 7 << 4); in sunxi_dw_hdmi_phy_init()
84 while ((readl(&phy->status) & 0x80) == 0) { in sunxi_dw_hdmi_phy_init()
86 printf("Warning: HDMI PHY init timeout!\n"); in sunxi_dw_hdmi_phy_init()
91 setbits_le32(&phy->ctrl, 0xf << 8); in sunxi_dw_hdmi_phy_init()
92 setbits_le32(&phy->ctrl, BIT(7)); in sunxi_dw_hdmi_phy_init()
94 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_init()
95 writel(0x80084343, &phy->clk); in sunxi_dw_hdmi_phy_init()
97 writel(1, &phy->unk3); in sunxi_dw_hdmi_phy_init()
98 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_init()
100 tmp = (readl(&phy->status) & 0x1f800) >> 11; in sunxi_dw_hdmi_phy_init()
101 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_init()
102 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_init()
103 writel(0x01FF0F7F, &phy->ctrl); in sunxi_dw_hdmi_phy_init()
104 writel(0x80639000, &phy->unk1); in sunxi_dw_hdmi_phy_init()
105 writel(0x0F81C405, &phy->unk2); in sunxi_dw_hdmi_phy_init()
108 writel(0x54524545, &phy->read_en); in sunxi_dw_hdmi_phy_init()
110 writel(0x42494E47, &phy->unscramble); in sunxi_dw_hdmi_phy_init()
115 struct sunxi_hdmi_phy * const phy = in sunxi_dw_hdmi_get_plug_in_status() local
118 return !!(readl(&phy->status) & (1 << 19)); in sunxi_dw_hdmi_get_plug_in_status()
132 return -1; in sunxi_dw_hdmi_wait_for_hpd()
137 struct sunxi_hdmi_phy * const phy = in sunxi_dw_hdmi_phy_set() local
148 writel(0x30dc5fc0, &phy->pll); in sunxi_dw_hdmi_phy_set()
149 writel(0x800863C0 | (phy_div - 1), &phy->clk); in sunxi_dw_hdmi_phy_set()
151 writel(0x00000001, &phy->unk3); in sunxi_dw_hdmi_phy_set()
152 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
154 tmp = (readl(&phy->status) & 0x1f800) >> 11; in sunxi_dw_hdmi_phy_set()
155 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
157 setbits_le32(&phy->pll, tmp + 2); in sunxi_dw_hdmi_phy_set()
159 setbits_le32(&phy->pll, 0x3f); in sunxi_dw_hdmi_phy_set()
161 writel(0x01FFFF7F, &phy->ctrl); in sunxi_dw_hdmi_phy_set()
162 writel(0x8063b000, &phy->unk1); in sunxi_dw_hdmi_phy_set()
163 writel(0x0F8246B5, &phy->unk2); in sunxi_dw_hdmi_phy_set()
166 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
167 writel(0x80084380 | (phy_div - 1), &phy->clk); in sunxi_dw_hdmi_phy_set()
169 writel(0x00000001, &phy->unk3); in sunxi_dw_hdmi_phy_set()
170 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
172 tmp = (readl(&phy->status) & 0x1f800) >> 11; in sunxi_dw_hdmi_phy_set()
173 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
174 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
175 writel(0x01FFFF7F, &phy->ctrl); in sunxi_dw_hdmi_phy_set()
176 writel(0x8063a800, &phy->unk1); in sunxi_dw_hdmi_phy_set()
177 writel(0x0F81C485, &phy->unk2); in sunxi_dw_hdmi_phy_set()
180 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
181 writel(0x80084340 | (phy_div - 1), &phy->clk); in sunxi_dw_hdmi_phy_set()
183 writel(0x00000001, &phy->unk3); in sunxi_dw_hdmi_phy_set()
184 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
186 tmp = (readl(&phy->status) & 0x1f800) >> 11; in sunxi_dw_hdmi_phy_set()
187 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
188 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
189 writel(0x01FFFF7F, &phy->ctrl); in sunxi_dw_hdmi_phy_set()
190 writel(0x8063b000, &phy->unk1); in sunxi_dw_hdmi_phy_set()
191 writel(0x0F81C405, &phy->unk2); in sunxi_dw_hdmi_phy_set()
194 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
195 writel(0x80084300 | (phy_div - 1), &phy->clk); in sunxi_dw_hdmi_phy_set()
197 writel(0x00000001, &phy->unk3); in sunxi_dw_hdmi_phy_set()
198 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
200 tmp = (readl(&phy->status) & 0x1f800) >> 11; in sunxi_dw_hdmi_phy_set()
201 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
202 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
203 writel(0x01FFFF7F, &phy->ctrl); in sunxi_dw_hdmi_phy_set()
204 writel(0x8063b000, &phy->unk1); in sunxi_dw_hdmi_phy_set()
205 writel(0x0F81C405, &phy->unk2); in sunxi_dw_hdmi_phy_set()
212 int value, n, m, div, diff; in sunxi_dw_hdmi_pll_set() local
228 for (m = 1; m <= 16; m++) { in sunxi_dw_hdmi_pll_set()
229 n = (m * target) / 24000; in sunxi_dw_hdmi_pll_set()
232 value = (24000 * n) / m / div; in sunxi_dw_hdmi_pll_set()
233 diff = clk_khz - value; in sunxi_dw_hdmi_pll_set()
236 best_m = m; in sunxi_dw_hdmi_pll_set()
257 int div = clock_get_pll3() / edid->pixelclock.typ; in sunxi_dw_hdmi_lcdc_init()
264 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0); in sunxi_dw_hdmi_lcdc_init()
267 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0); in sunxi_dw_hdmi_lcdc_init()
269 &ccm->lcd0_clk_cfg); in sunxi_dw_hdmi_lcdc_init()
274 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1); in sunxi_dw_hdmi_lcdc_init()
277 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1); in sunxi_dw_hdmi_lcdc_init()
279 &ccm->lcd1_clk_cfg); in sunxi_dw_hdmi_lcdc_init()
301 return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size); in sunxi_dw_hdmi_read_edid()
307 struct sunxi_hdmi_phy * const phy = in sunxi_dw_hdmi_enable() local
312 ret = dw_hdmi_enable(&priv->hdmi, edid); in sunxi_dw_hdmi_enable()
316 sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp); in sunxi_dw_hdmi_enable()
318 if (edid->flags & DISPLAY_FLAGS_VSYNC_LOW) in sunxi_dw_hdmi_enable()
319 setbits_le32(&phy->pol, 0x200); in sunxi_dw_hdmi_enable()
321 if (edid->flags & DISPLAY_FLAGS_HSYNC_LOW) in sunxi_dw_hdmi_enable()
322 setbits_le32(&phy->pol, 0x100); in sunxi_dw_hdmi_enable()
324 setbits_le32(&phy->ctrl, 0xf << 12); in sunxi_dw_hdmi_enable()
332 writel(0, &phy->unscramble); in sunxi_dw_hdmi_enable()
349 clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK, in sunxi_dw_hdmi_probe()
353 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_dw_hdmi_probe()
354 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2); in sunxi_dw_hdmi_probe()
355 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); in sunxi_dw_hdmi_probe()
356 setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE); in sunxi_dw_hdmi_probe()
359 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); in sunxi_dw_hdmi_probe()
366 return -1; in sunxi_dw_hdmi_probe()
369 priv->hdmi.ioaddr = SUNXI_HDMI_BASE; in sunxi_dw_hdmi_probe()
370 priv->hdmi.i2c_clk_high = 0xd8; in sunxi_dw_hdmi_probe()
371 priv->hdmi.i2c_clk_low = 0xfe; in sunxi_dw_hdmi_probe()
372 priv->hdmi.reg_io_width = 1; in sunxi_dw_hdmi_probe()
373 priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg; in sunxi_dw_hdmi_probe()
374 priv->mux = uc_plat->source_id; in sunxi_dw_hdmi_probe()
376 dw_hdmi_init(&priv->hdmi); in sunxi_dw_hdmi_probe()