Lines Matching +full:video +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0+
15 #include <video.h>
20 #include <dm/device-internal.h>
21 #include <dm/uclass-internal.h>
41 /* set SRAM for video use (A64 only) */ in sunxi_de2_composer_init()
50 clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK, in sunxi_de2_composer_init()
54 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE); in sunxi_de2_composer_init()
55 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE); in sunxi_de2_composer_init()
58 setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE); in sunxi_de2_composer_init()
61 static void sunxi_de2_mode_set(int mux, const struct display_timing *mode, in sunxi_de2_mode_set() argument
64 ulong de_mux_base = (mux == 0) ? in sunxi_de2_mode_set()
81 u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ); in sunxi_de2_mode_set()
87 setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4); in sunxi_de2_mode_set()
89 setbits_le32(&de_clk_regs->rst_cfg, BIT(mux)); in sunxi_de2_mode_set()
91 setbits_le32(&de_clk_regs->gate_cfg, BIT(mux)); in sunxi_de2_mode_set()
92 setbits_le32(&de_clk_regs->bus_cfg, BIT(mux)); in sunxi_de2_mode_set()
94 clrbits_le32(&de_clk_regs->sel_cfg, 1); in sunxi_de2_mode_set()
96 writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl); in sunxi_de2_mode_set()
97 writel(0, &de_glb_regs->status); in sunxi_de2_mode_set()
98 writel(1, &de_glb_regs->dbuff); in sunxi_de2_mode_set()
99 writel(size, &de_glb_regs->size); in sunxi_de2_mode_set()
109 writel(0x00000101, &de_bld_regs->fcolor_ctl); in sunxi_de2_mode_set()
111 writel(1, &de_bld_regs->route); in sunxi_de2_mode_set()
113 writel(0, &de_bld_regs->premultiply); in sunxi_de2_mode_set()
114 writel(0xff000000, &de_bld_regs->bkcolor); in sunxi_de2_mode_set()
116 writel(0x03010301, &de_bld_regs->bld_mode[0]); in sunxi_de2_mode_set()
118 writel(size, &de_bld_regs->output_size); in sunxi_de2_mode_set()
119 writel(mode->flags & DISPLAY_FLAGS_INTERLACED ? 2 : 0, in sunxi_de2_mode_set()
120 &de_bld_regs->out_ctl); in sunxi_de2_mode_set()
121 writel(0, &de_bld_regs->ck_ctl); in sunxi_de2_mode_set()
123 writel(0xff000000, &de_bld_regs->attr[0].fcolor); in sunxi_de2_mode_set()
124 writel(size, &de_bld_regs->attr[0].insize); in sunxi_de2_mode_set()
140 writel(0x107, &de_csc_regs->coef11); in sunxi_de2_mode_set()
141 writel(0x204, &de_csc_regs->coef12); in sunxi_de2_mode_set()
142 writel(0x64, &de_csc_regs->coef13); in sunxi_de2_mode_set()
143 writel(0x4200, &de_csc_regs->coef14); in sunxi_de2_mode_set()
144 writel(0x1f68, &de_csc_regs->coef21); in sunxi_de2_mode_set()
145 writel(0x1ed6, &de_csc_regs->coef22); in sunxi_de2_mode_set()
146 writel(0x1c2, &de_csc_regs->coef23); in sunxi_de2_mode_set()
147 writel(0x20200, &de_csc_regs->coef24); in sunxi_de2_mode_set()
148 writel(0x1c2, &de_csc_regs->coef31); in sunxi_de2_mode_set()
149 writel(0x1e87, &de_csc_regs->coef32); in sunxi_de2_mode_set()
150 writel(0x1fb7, &de_csc_regs->coef33); in sunxi_de2_mode_set()
151 writel(0x20200, &de_csc_regs->coef34); in sunxi_de2_mode_set()
154 writel(1, &de_csc_regs->csc_ctl); in sunxi_de2_mode_set()
156 writel(0, &de_csc_regs->csc_ctl); in sunxi_de2_mode_set()
169 writel(SUNXI_DE2_UI_CFG_ATTR_EN | format, &de_ui_regs->cfg[0].attr); in sunxi_de2_mode_set()
170 writel(size, &de_ui_regs->cfg[0].size); in sunxi_de2_mode_set()
171 writel(0, &de_ui_regs->cfg[0].coord); in sunxi_de2_mode_set()
172 writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch); in sunxi_de2_mode_set()
173 writel(address, &de_ui_regs->cfg[0].top_laddr); in sunxi_de2_mode_set()
174 writel(size, &de_ui_regs->ovl_size); in sunxi_de2_mode_set()
177 writel(1, &de_glb_regs->dbuff); in sunxi_de2_mode_set()
182 struct udevice *disp, int mux, bool is_composite) in sunxi_de2_init() argument
190 debug("Using device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat); in sunxi_de2_init()
192 debug(" - device in use\n"); in sunxi_de2_init()
193 return -EBUSY; in sunxi_de2_init()
196 disp_uc_plat->source_id = mux; in sunxi_de2_init()
201 __func__, dev->name, ret); in sunxi_de2_init()
212 sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase, is_composite); in sunxi_de2_init()
220 uc_priv->xsize = timing.hactive.typ; in sunxi_de2_init()
221 uc_priv->ysize = timing.vactive.typ; in sunxi_de2_init()
222 uc_priv->bpix = l2bpp; in sunxi_de2_init()
223 debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize); in sunxi_de2_init()
242 if (!(gd->flags & GD_FLG_RELOC)) in sunxi_de2_probe()
248 int mux; in sunxi_de2_probe() local
250 mux = 0; in sunxi_de2_probe()
252 ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux, in sunxi_de2_probe()
265 int mux; in sunxi_de2_probe() local
267 mux = 0; in sunxi_de2_probe()
269 mux = 1; in sunxi_de2_probe()
271 ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux, in sunxi_de2_probe()
288 ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, 1, true); in sunxi_de2_probe()
301 plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT * in sunxi_de2_bind()
332 int mux; in sunxi_simplefb_setup() local
340 mux = 0; in sunxi_simplefb_setup()
342 mux = 1; in sunxi_simplefb_setup()
360 if (mux == 0) in sunxi_simplefb_setup()
361 pipeline = "mixer0-lcd0-hdmi"; in sunxi_simplefb_setup()
363 pipeline = "mixer1-lcd1-hdmi"; in sunxi_simplefb_setup()
373 pipeline = "mixer0-lcd0"; in sunxi_simplefb_setup()
391 start = gd->bd->bi_dram[0].start; in sunxi_simplefb_setup()
392 size = de2_plat->base - start; in sunxi_simplefb_setup()
399 ret = fdt_setup_simplefb_node(blob, offset, de2_plat->base, in sunxi_simplefb_setup()
400 de2_priv->xsize, de2_priv->ysize, in sunxi_simplefb_setup()
401 VNBYTES(de2_priv->bpix) * de2_priv->xsize, in sunxi_simplefb_setup()