Lines Matching +full:0 +full:xc5

41 #define SCF0403852GGU04_ID 0x000080
44 static u16 extcmd_params_sn20[] = {0xff, 0x98, 0x06};
45 static u16 spiinttype_params_sn20[] = {0x60};
47 0x01, 0x10, 0x61, 0x74, 0x01, 0x01, 0x1B,
48 0x12, 0x71, 0x00, 0x00, 0x00, 0x01, 0x01,
49 0x05, 0x00, 0xFF, 0xF2, 0x01, 0x00, 0x40,
51 static u16 bd_params_sn20[] = {0x01, 0x23, 0x45, 0x67, 0x01, 0x23, 0x45, 0x67};
53 0x01, 0x22, 0x22, 0xBA, 0xDC, 0x26, 0x28, 0x22, 0x22,
55 static u16 vcom_params_sn20[] = {0x74};
56 static u16 vmesur_params_sn20[] = {0x7F, 0x0F, 0x00};
57 static u16 powerctl_params_sn20[] = {0x03, 0x0b, 0x00};
58 static u16 lvglvolt_params_sn20[] = {0x08};
59 static u16 engsetting_params_sn20[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x20};
60 static u16 dispfunc_params_sn20[] = {0xa0};
61 static u16 dvddvolt_params_sn20[] = {0x74};
62 static u16 dispinv_params_sn20[] = {0x00, 0x00, 0x00};
63 static u16 panelres_params_sn20[] = {0x82};
64 static u16 framerate_params_sn20[] = {0x00, 0x13, 0x13};
65 static u16 timing_params_sn20[] = {0x80, 0x05, 0x40, 0x28};
66 static u16 powerctl2_params_sn20[] = {0x17, 0x75, 0x79, 0x20};
67 static u16 memaccess_params_sn20[] = {0x00};
68 static u16 pixfmt_params_sn20[] = {0x66};
70 0x00, 0x03, 0x0b, 0x0c, 0x0e, 0x08, 0xc5, 0x04,
71 0x08, 0x0c, 0x13, 0x11, 0x11, 0x14, 0x0c, 0x10,
74 0x00, 0x0d, 0x11, 0x0c, 0x0c, 0x04, 0x76, 0x03,
75 0x08, 0x0b, 0x16, 0x10, 0x0d, 0x16, 0x0a, 0x00,
77 static u16 tearing_params_sn20[] = {0x00};
80 static u16 memaccess_params_sn04[] = {0x08};
81 static u16 pixfmt_params_sn04[] = {0x66};
82 static u16 modectl_params_sn04[] = {0x01};
83 static u16 dispfunc_params_sn04[] = {0x22, 0xe2, 0xFF, 0x04};
84 static u16 vcom_params_sn04[] = {0x00, 0x6A};
86 0x00, 0x07, 0x0d, 0x10, 0x13, 0x19, 0x0f, 0x0c,
87 0x05, 0x08, 0x06, 0x13, 0x0f, 0x30, 0x20, 0x1f,
90 0x1F, 0x20, 0x30, 0x0F, 0x13, 0x06, 0x08, 0x05,
91 0x0C, 0x0F, 0x19, 0x13, 0x10, 0x0D, 0x07, 0x00,
93 static u16 dispinv_params_sn04[] = {0x02};
96 static struct scf0403_cmd scf0403_cmd_slpout = {0x11, NULL, 0};
97 static struct scf0403_cmd scf0403_cmd_dison = {0x29, NULL, 0};
101 {{0x36, memaccess_params_sn04, ARRAY_SIZE(memaccess_params_sn04)}, 0},
102 {{0x3A, pixfmt_params_sn04, ARRAY_SIZE(pixfmt_params_sn04)}, 0},
103 {{0xB6, dispfunc_params_sn04, ARRAY_SIZE(dispfunc_params_sn04)}, 0},
104 {{0xC5, vcom_params_sn04, ARRAY_SIZE(vcom_params_sn04)}, 0},
105 {{0xE0, pgamma_params_sn04, ARRAY_SIZE(pgamma_params_sn04)}, 0},
106 {{0xE1, ngamma_params_sn04, ARRAY_SIZE(ngamma_params_sn04)}, 20},
107 {{0xB0, modectl_params_sn04, ARRAY_SIZE(modectl_params_sn04)}, 0},
108 {{0xB4, dispinv_params_sn04, ARRAY_SIZE(dispinv_params_sn04)}, 100},
113 {{0xff, extcmd_params_sn20, ARRAY_SIZE(extcmd_params_sn20)}, 0},
114 {{0xba, spiinttype_params_sn20, ARRAY_SIZE(spiinttype_params_sn20)}, 0},
115 {{0xbc, bc_params_sn20, ARRAY_SIZE(bc_params_sn20)}, 0},
116 {{0xbd, bd_params_sn20, ARRAY_SIZE(bd_params_sn20)}, 0},
117 {{0xbe, be_params_sn20, ARRAY_SIZE(be_params_sn20)}, 0},
118 {{0xc7, vcom_params_sn20, ARRAY_SIZE(vcom_params_sn20)}, 0},
119 {{0xed, vmesur_params_sn20, ARRAY_SIZE(vmesur_params_sn20)}, 0},
120 {{0xc0, powerctl_params_sn20, ARRAY_SIZE(powerctl_params_sn20)}, 0},
121 {{0xfc, lvglvolt_params_sn20, ARRAY_SIZE(lvglvolt_params_sn20)}, 0},
122 {{0xb6, dispfunc_params_sn20, ARRAY_SIZE(dispfunc_params_sn20)}, 0},
123 {{0xdf, engsetting_params_sn20, ARRAY_SIZE(engsetting_params_sn20)}, 0},
124 {{0xf3, dvddvolt_params_sn20, ARRAY_SIZE(dvddvolt_params_sn20)}, 0},
125 {{0xb4, dispinv_params_sn20, ARRAY_SIZE(dispinv_params_sn20)}, 0},
126 {{0xf7, panelres_params_sn20, ARRAY_SIZE(panelres_params_sn20)}, 0},
127 {{0xb1, framerate_params_sn20, ARRAY_SIZE(framerate_params_sn20)}, 0},
128 {{0xf2, timing_params_sn20, ARRAY_SIZE(timing_params_sn20)}, 0},
129 {{0xc1, powerctl2_params_sn20, ARRAY_SIZE(powerctl2_params_sn20)}, 0},
130 {{0x36, memaccess_params_sn20, ARRAY_SIZE(memaccess_params_sn20)}, 0},
131 {{0x3a, pixfmt_params_sn20, ARRAY_SIZE(pixfmt_params_sn20)}, 0},
132 {{0xe0, pgamma_params_sn20, ARRAY_SIZE(pgamma_params_sn20)}, 0},
133 {{0xe1, ngamma_params_sn20, ARRAY_SIZE(ngamma_params_sn20)}, 0},
134 {{0x35, tearing_params_sn20, ARRAY_SIZE(tearing_params_sn20)}, 0},
144 gpio_set_value(gpio, 0); in scf0403_gpio_reset()
152 int error = 0; in scf0403_spi_read_rddid()
153 u8 ids_buf = 0x00; in scf0403_spi_read_rddid()
154 u16 dummy_buf = 0x00; in scf0403_spi_read_rddid()
155 u16 cmd = 0x04; in scf0403_spi_read_rddid()
186 return 0; in scf0403_spi_read_rddid()
203 for (i = 0; i < cmd->count; i++) { in scf0403_spi_transfer()
204 msg = (cmd->params[i] | 0x100); in scf0403_spi_transfer()
210 return 0; in scf0403_spi_transfer()
220 for (i = 0; i < priv->seq_size; i++) { in scf0403_lcd_init()
221 if (scf0403_spi_transfer(priv->spi, &priv->init_seq[i].cmd) < 0) in scf0403_lcd_init()
235 err = gpio_direction_output(gpio, 0); in scf0403_request_reset_gpio()
256 priv.spi = spi_setup_slave(3, 0, 1000000, SPI_MODE_0); in scf0403_init()
286 return 0; in scf0403_init()