Lines Matching +full:0 +full:x2e00
14 #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
15 #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
16 #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */
28 0x15561500, 0x14561600, 0x13561700, 0x12561800,
29 0x11551a00, 0x11541b00, 0x10541c00, 0x0f541d00,
30 0x0f531e00, 0x0e531f00, 0x0d522100, 0x0c522200,
31 0x0b522300, 0x0b512400, 0x0a502600, 0x0a4f2700,
32 0x094e2900, 0x084e2a00, 0x084d2b00, 0x074c2c01,
33 0x074b2d01, 0x064a2f01, 0x06493001, 0x05483201,
34 0x05473301, 0x05463401, 0x04453601, 0x04433702,
35 0x04423802, 0x03413a02, 0x03403b02, 0x033f3c02,
36 0x033d3d03
45 writel(is_horizontal ? BIT(8) : 0, in meson_vpp_write_scaling_filter_coefs()
47 for (i = 0; i < 33; i++) in meson_vpp_write_scaling_filter_coefs()
53 0x00800000, 0x007f0100, 0xff7f0200, 0xfe7f0300,
54 0xfd7e0500, 0xfc7e0600, 0xfb7d0800, 0xfb7c0900,
55 0xfa7b0b00, 0xfa7a0dff, 0xf9790fff, 0xf97711ff,
56 0xf87613ff, 0xf87416fe, 0xf87218fe, 0xf8701afe,
57 0xf76f1dfd, 0xf76d1ffd, 0xf76b21fd, 0xf76824fd,
58 0xf76627fc, 0xf76429fc, 0xf7612cfc, 0xf75f2ffb,
59 0xf75d31fb, 0xf75a34fb, 0xf75837fa, 0xf7553afa,
60 0xf8523cfa, 0xf8503ff9, 0xf84d42f9, 0xf84a45f9,
61 0xf84848f8
70 writel(is_horizontal ? BIT(8) : 0, in meson_vpp_write_vd_scaling_filter_coefs()
72 for (i = 0; i < 33; i++) in meson_vpp_write_vd_scaling_filter_coefs()
80 VIU_MATRIX_OSD_EOTF = 0,
85 VIU_LUT_OSD_EOTF = 0,
97 0, 0, 0, /* pre offset */
101 0, 0, 0, /* 10'/11'/12' */
102 0, 0, 0, /* 20'/21'/22' */
104 0, 0, 0 /* mode, right_shift, clip_en */
121 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_osd_matrix()
123 writel(m[2] & 0xfff, in meson_viu_set_osd_matrix()
125 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_osd_matrix()
127 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_osd_matrix()
129 writel(((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff), in meson_viu_set_osd_matrix()
131 writel(((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff), in meson_viu_set_osd_matrix()
135 writel(((m[11] & 0x1fff) << 16) | (m[12] & 0x1fff), in meson_viu_set_osd_matrix()
138 writel(((m[13] & 0x1fff) << 16) | (m[14] & 0x1fff), in meson_viu_set_osd_matrix()
141 writel(((m[15] & 0x1fff) << 16) | (m[16] & 0x1fff), in meson_viu_set_osd_matrix()
144 writel(m[17] & 0x1fff, priv->io_base + in meson_viu_set_osd_matrix()
147 writel((m[11] & 0x1fff) << 16, priv->io_base + in meson_viu_set_osd_matrix()
151 writel(((m[18] & 0xfff) << 16) | (m[19] & 0xfff), in meson_viu_set_osd_matrix()
153 writel(m[20] & 0xfff, in meson_viu_set_osd_matrix()
164 writel_bits(BIT(0), csc_on ? BIT(0) : 0, in meson_viu_set_osd_matrix()
166 writel_bits(BIT(1), 0, in meson_viu_set_osd_matrix()
172 for (i = 0; i < 5; i++) in meson_viu_set_osd_matrix()
173 writel(((m[i * 2] & 0x1fff) << 16) | in meson_viu_set_osd_matrix()
174 (m[i * 2 + 1] & 0x1fff), priv->io_base + in meson_viu_set_osd_matrix()
177 writel_bits(BIT(30), csc_on ? BIT(30) : 0, in meson_viu_set_osd_matrix()
179 writel_bits(BIT(31), csc_on ? BIT(31) : 0, in meson_viu_set_osd_matrix()
211 writel(0, priv->io_base + _REG(addr_port)); in meson_viu_set_osd_lut()
213 for (i = 0; i < 20; i++) in meson_viu_set_osd_lut()
217 writel(r_map[OSD_OETF_LUT_SIZE - 1] | (g_map[0] << 16), in meson_viu_set_osd_lut()
220 for (i = 0; i < 20; i++) in meson_viu_set_osd_lut()
224 for (i = 0; i < 20; i++) in meson_viu_set_osd_lut()
232 writel_bits(0x7 << 29, 7 << 29, in meson_viu_set_osd_lut()
235 writel_bits(0x7 << 29, 0, in meson_viu_set_osd_lut()
238 writel(0, priv->io_base + _REG(addr_port)); in meson_viu_set_osd_lut()
240 for (i = 0; i < 20; i++) in meson_viu_set_osd_lut()
244 writel(r_map[OSD_EOTF_LUT_SIZE - 1] | (g_map[0] << 16), in meson_viu_set_osd_lut()
247 for (i = 0; i < 20; i++) in meson_viu_set_osd_lut()
251 for (i = 0; i < 20; i++) in meson_viu_set_osd_lut()
262 writel_bits(7 << 27, 0, in meson_viu_set_osd_lut()
272 0x0000, 0x0200, 0x0400, 0x0600,
273 0x0800, 0x0a00, 0x0c00, 0x0e00,
274 0x1000, 0x1200, 0x1400, 0x1600,
275 0x1800, 0x1a00, 0x1c00, 0x1e00,
276 0x2000, 0x2200, 0x2400, 0x2600,
277 0x2800, 0x2a00, 0x2c00, 0x2e00,
278 0x3000, 0x3200, 0x3400, 0x3600,
279 0x3800, 0x3a00, 0x3c00, 0x3e00,
280 0x4000
285 0, 0, 0, 0,
286 0, 32, 64, 96,
331 writel(0x210000, priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); in meson_vpu_init()
332 writel(0x10000, priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); in meson_vpu_init()
333 writel(0x900000, priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); in meson_vpu_init()
334 writel(0x20000, priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); in meson_vpu_init()
337 hhi_write(HHI_VDAC_CNTL0, 0); in meson_vpu_init()
341 writel(0xff, priv->io_base + _REG(VENC_VDAC_SETTING)); in meson_vpu_init()
344 hhi_write(HHI_HDMI_PHY_CNTL0, 0); in meson_vpu_init()
347 writel_bits(0x3, 0, priv->io_base + _REG(VPU_HDMI_SETTING)); in meson_vpu_init()
350 writel(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_vpu_init()
351 writel(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_vpu_init()
352 writel(0, priv->io_base + _REG(ENCL_VIDEO_EN)); in meson_vpu_init()
355 writel(0, priv->io_base + _REG(VENC_INTCTRL)); in meson_vpu_init()
359 writel(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpu_init()
361 writel_bits(0xff << 16, 0xff << 16, in meson_vpu_init()
363 writel(0x20000, priv->io_base + _REG(VPP_DOLBY_CTRL)); in meson_vpu_init()
364 writel(0x1020080, in meson_vpu_init()
370 0x77f, priv->io_base + _REG(VPP_OFIFO_SIZE)); in meson_vpu_init()
371 writel(0x08080808, priv->io_base + _REG(VPP_HOLD_LINES)); in meson_vpu_init()
374 writel_bits(VPP_PREBLEND_ENABLE, 0, in meson_vpu_init()
378 writel_bits(VPP_POSTBLEND_ENABLE, 0, in meson_vpu_init()
384 VPP_VD1_PREBLEND | VPP_VD2_PREBLEND, 0, in meson_vpu_init()
394 writel(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0)); in meson_vpu_init()
395 writel(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0)); in meson_vpu_init()
396 writel(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0)); in meson_vpu_init()
413 writel_bits(BIT(0) | BIT(21), 0, in meson_vpu_init()
415 writel_bits(BIT(0) | BIT(21), 0, in meson_vpu_init()
424 reg = BIT(0) | /* Urgent DDR request priority */ in meson_vpu_init()
434 writel_bits(0xff << OSD_REPLACE_SHIFT, in meson_vpu_init()
435 0xff << OSD_REPLACE_SHIFT, in meson_vpu_init()
437 writel_bits(0xff << OSD_REPLACE_SHIFT, in meson_vpu_init()
438 0xff << OSD_REPLACE_SHIFT, in meson_vpu_init()