105 	hhi_update_bits(HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0);  in meson_vid_pll_set()
106 	hhi_update_bits(HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0);  in meson_vid_pll_set()
169 		hhi_update_bits(HHI_VID_PLL_CLK_DIV,  in meson_vid_pll_set()
173 		hhi_update_bits(HHI_VID_PLL_CLK_DIV,  in meson_vid_pll_set()
176 		hhi_update_bits(HHI_VID_PLL_CLK_DIV,  in meson_vid_pll_set()
178 		hhi_update_bits(HHI_VID_PLL_CLK_DIV,  in meson_vid_pll_set()
180 		hhi_update_bits(HHI_VID_PLL_CLK_DIV,  in meson_vid_pll_set()
184 		hhi_update_bits(HHI_VID_PLL_CLK_DIV,  in meson_vid_pll_set()
186 		hhi_update_bits(HHI_VID_PLL_CLK_DIV,  in meson_vid_pll_set()
188 		hhi_update_bits(HHI_VID_PLL_CLK_DIV,  in meson_vid_pll_set()
191 		hhi_update_bits(HHI_VID_PLL_CLK_DIV,  in meson_vid_pll_set()
196 	hhi_update_bits(HHI_VID_PLL_CLK_DIV,  in meson_vid_pll_set()
230 		hhi_update_bits(HHI_HDMI_PLL_CNTL,  in meson_venci_cvbs_clock_config()
232 		hhi_update_bits(HHI_HDMI_PLL_CNTL,  in meson_venci_cvbs_clock_config()
243 	hhi_update_bits(HHI_VIID_CLK_CNTL, VCLK2_EN, 0);  in meson_venci_cvbs_clock_config()
249 	hhi_update_bits(HHI_VIID_CLK_DIV,  in meson_venci_cvbs_clock_config()
253 	hhi_update_bits(HHI_VIID_CLK_CNTL,  in meson_venci_cvbs_clock_config()
256 	hhi_update_bits(HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);  in meson_venci_cvbs_clock_config()
259 	hhi_update_bits(HHI_VID_CLK_DIV,  in meson_venci_cvbs_clock_config()
262 	hhi_update_bits(HHI_VIID_CLK_DIV,  in meson_venci_cvbs_clock_config()
266 	hhi_update_bits(HHI_VIID_CLK_DIV,  in meson_venci_cvbs_clock_config()
270 	hhi_update_bits(HHI_VIID_CLK_CNTL,  in meson_venci_cvbs_clock_config()
274 	hhi_update_bits(HHI_VIID_CLK_CNTL,  in meson_venci_cvbs_clock_config()
276 	hhi_update_bits(HHI_VIID_CLK_CNTL,  in meson_venci_cvbs_clock_config()
280 	hhi_update_bits(HHI_VID_CLK_CNTL2,  in meson_venci_cvbs_clock_config()
283 	hhi_update_bits(HHI_VID_CLK_CNTL2,  in meson_venci_cvbs_clock_config()
410 		hhi_update_bits(HHI_HDMI_PLL_CNTL,  in meson_hdmi_pll_set_params()
426 		hhi_update_bits(HHI_HDMI_PLL_CNTL,  in meson_hdmi_pll_set_params()
428 		hhi_update_bits(HHI_HDMI_PLL_CNTL,  in meson_hdmi_pll_set_params()
437 		hhi_update_bits(HHI_HDMI_PLL_CNTL2,  in meson_hdmi_pll_set_params()
441 		hhi_update_bits(HHI_HDMI_PLL_CNTL3,  in meson_hdmi_pll_set_params()
445 		hhi_update_bits(HHI_HDMI_PLL_CNTL2,  in meson_hdmi_pll_set_params()
449 		hhi_update_bits(HHI_HDMI_PLL_CNTL3,  in meson_hdmi_pll_set_params()
453 		hhi_update_bits(HHI_HDMI_PLL_CNTL2,  in meson_hdmi_pll_set_params()
457 		hhi_update_bits(HHI_HDMI_PLL_CNTL3,  in meson_hdmi_pll_set_params()
601 	hhi_update_bits(HHI_HDMI_CLK_CNTL,  in meson_vclk_set()
603 	hhi_update_bits(HHI_HDMI_CLK_CNTL,  in meson_vclk_set()
605 	hhi_update_bits(HHI_HDMI_CLK_CNTL,  in meson_vclk_set()
648 	hhi_update_bits(HHI_VID_CLK_CNTL,  in meson_vclk_set()
650 	hhi_update_bits(HHI_VID_CLK_DIV,  in meson_vclk_set()
657 		hhi_update_bits(HHI_VID_CLK_CNTL,  in meson_vclk_set()
661 		hhi_update_bits(HHI_HDMI_CLK_CNTL,  in meson_vclk_set()
666 		hhi_update_bits(HHI_VID_CLK_CNTL,  in meson_vclk_set()
670 		hhi_update_bits(HHI_HDMI_CLK_CNTL,  in meson_vclk_set()
676 		hhi_update_bits(HHI_VID_CLK_CNTL,  in meson_vclk_set()
680 		hhi_update_bits(HHI_HDMI_CLK_CNTL,  in meson_vclk_set()
686 		hhi_update_bits(HHI_VID_CLK_CNTL,  in meson_vclk_set()
690 		hhi_update_bits(HHI_HDMI_CLK_CNTL,  in meson_vclk_set()
696 		hhi_update_bits(HHI_VID_CLK_CNTL,  in meson_vclk_set()
700 		hhi_update_bits(HHI_HDMI_CLK_CNTL,  in meson_vclk_set()
705 	hhi_update_bits(HHI_VID_CLK_CNTL2,  in meson_vclk_set()
712 		hhi_update_bits(HHI_VID_CLK_CNTL,  in meson_vclk_set()
717 			hhi_update_bits(HHI_VID_CLK_DIV,  in meson_vclk_set()
721 			hhi_update_bits(HHI_VID_CLK_DIV,  in meson_vclk_set()
726 		hhi_update_bits(HHI_VID_CLK_CNTL,  in meson_vclk_set()
731 			hhi_update_bits(HHI_VID_CLK_DIV,  in meson_vclk_set()
736 			hhi_update_bits(HHI_VID_CLK_DIV,  in meson_vclk_set()
742 		hhi_update_bits(HHI_VID_CLK_CNTL,  in meson_vclk_set()
747 			hhi_update_bits(HHI_VID_CLK_DIV,  in meson_vclk_set()
752 			hhi_update_bits(HHI_VID_CLK_DIV,  in meson_vclk_set()
758 		hhi_update_bits(HHI_VID_CLK_CNTL,  in meson_vclk_set()
763 			hhi_update_bits(HHI_VID_CLK_DIV,  in meson_vclk_set()
768 			hhi_update_bits(HHI_VID_CLK_DIV,  in meson_vclk_set()
774 		hhi_update_bits(HHI_VID_CLK_CNTL,  in meson_vclk_set()
779 			hhi_update_bits(HHI_VID_CLK_DIV,  in meson_vclk_set()
784 			hhi_update_bits(HHI_VID_CLK_DIV,  in meson_vclk_set()
792 		hhi_update_bits(HHI_VID_CLK_CNTL2,  in meson_vclk_set()
796 		hhi_update_bits(HHI_VID_CLK_CNTL2,  in meson_vclk_set()
799 	hhi_update_bits(HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);  in meson_vclk_set()