1 // SPDX-License-Identifier: GPL-2.0
24 #define HHI_VID_PLL_CLK_DIV	0x1a0 /* 0x68 offset in data sheet */
28 #define HHI_VIID_CLK_DIV	0x128 /* 0x4a offset in data sheet */
34 #define HHI_VIID_CLK_CNTL	0x12c /* 0x4b offset in data sheet */
40 #define HHI_VID_CLK_DIV		0x164 /* 0x59 offset in data sheet */
48 #define HHI_VID_CLK_CNTL	0x17c /* 0x5f offset in data sheet */
58 #define HHI_VID_CLK_CNTL2	0x194 /* 0x65 offset in data sheet */
63 #define HHI_HDMI_CLK_CNTL	0x1cc /* 0x73 offset in data sheet */
70 #define HHI_HDMI_PLL_CNTL	0x320 /* 0xc8 offset in data sheet */
71 #define HHI_HDMI_PLL_CNTL2	0x324 /* 0xc9 offset in data sheet */
72 #define HHI_HDMI_PLL_CNTL3	0x328 /* 0xca offset in data sheet */
73 #define HHI_HDMI_PLL_CNTL4	0x32C /* 0xcb offset in data sheet */
74 #define HHI_HDMI_PLL_CNTL5	0x330 /* 0xcc offset in data sheet */
75 #define HHI_HDMI_PLL_CNTL6	0x334 /* 0xcd offset in data sheet */
239 	readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,  in meson_venci_cvbs_clock_config()
250 			VCLK2_DIV_MASK, (55 - 1));  in meson_venci_cvbs_clock_config()
414 		readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,  in meson_hdmi_pll_set_params()
432 		readl_poll_timeout(priv->hhi_base + HHI_HDMI_PLL_CNTL, val,  in meson_hdmi_pll_set_params()
466 	/* The GXBB PLL has a /2 pre-multiplier */  in meson_hdmi_pll_get_m()
485 	/* The GXBB PLL has a /2 pre-multiplier and a larger FRAC width */  in meson_hdmi_pll_get_frac()
500 	frac -= frac_m;  in meson_hdmi_pll_get_frac()
502 	return min((u16)frac, (u16)(frac_max - 1));  in meson_hdmi_pll_get_frac()
600 	/* Set HDMI-TX sys clock */  in meson_vclk_set()
651 			VCLK_DIV_MASK, vclk_div - 1);  in meson_vclk_set()
653 	/* Set HDMI-TX source */  in meson_vclk_set()
660 		/* select vclk_div1 for HDMI-TX */  in meson_vclk_set()
669 		/* select vclk_div2 for HDMI-TX */  in meson_vclk_set()
679 		/* select vclk_div4 for HDMI-TX */  in meson_vclk_set()
689 		/* select vclk_div6 for HDMI-TX */  in meson_vclk_set()
699 		/* select vclk_div12 for HDMI-TX */  in meson_vclk_set()
815 		 * - automatic PLL freq + OD management  in meson_vclk_setup()
816 		 * - vid_pll_div = VID_PLL_DIV_5  in meson_vclk_setup()
817 		 * - vclk_div = 2  in meson_vclk_setup()
818 		 * - hdmi_tx_div = 1  in meson_vclk_setup()
819 		 * - venc_div = 1  in meson_vclk_setup()
820 		 * - encp encoder  in meson_vclk_setup()
831 		printf("Fatal Error, invalid HDMI-TX freq %d\n",  in meson_vclk_setup()
889 	vclk_freq = mode->pixelclock.typ / 1000;  in meson_vpu_setup_vclk()