video/meson/meson_dw_hdmi.h

1 /* SPDX-License-Identifier: GPL-2.0 */
35  * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0.
36  * Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0.
37  * Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0.
38  * Bit 1 RW tmds_clk_en: 1=enable tmds_clk;  0=disable. Default 0.
39  * Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0.
51  *     1=Enable interrupt source; 0=Disable interrupt source. Default 0.
83 /* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
84  *     3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0.
87  * Bit 8 RW shift_pttn_en: 1= Enable shift pattern generator; 0=Disable.
90  * Bit 2: 1 RW prbs_pttn_width: 0=idle; 1=output 8-bit pattern;
91  *     2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0.
92  * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0.