Lines Matching full:default

12  * Bit 7 RW Reserved. Default 1.
13  * Bit 6 RW Reserved. Default 1.
14  * Bit 5 RW Reserved. Default 1.
16  *     Default 1.
19  *     Default 1.
21  *     Default 1.
23  *     0=Release from reset. Default 1.
25  *     0=Release from reset. Default 1.
30  * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
31  * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0.
32  * Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0.
33  * Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0.
34  * Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0.
35  * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0.
36  * Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0.
37  * Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0.
38  * Bit 1 RW tmds_clk_en: 1=enable tmds_clk;  0=disable. Default 0.
39  * Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0.
44  * Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024.    Default 0.
45  * Bit 15:12 RW hpd_glitch_width: filter out glitch <= N.       Default 0.
51  *     1=Enable interrupt source; 0=Disable interrupt source. Default 0.
84  *     3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0.
86  *     every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0.
88  *     Default 0.
89  * Bit 4: 3 RW prbs_pttn_mode: 0=PRBS11; 1=PRBS15; 2=PRBS7; 3=PRBS31. Default 0.
91  *     2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0.
92  * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0.
96 /* Bit 29:20 RW shift_pttn_data[59:50]. Default 0. */
97 /* Bit 19:10 RW shift_pttn_data[69:60]. Default 0. */
98 /* Bit  9: 0 RW shift_pttn_data[79:70]. Default 0. */
101 /* Bit 29:20 RW shift_pttn_data[29:20]. Default 0. */
102 /* Bit 19:10 RW shift_pttn_data[39:30]. Default 0. */
103 /* Bit  9: 0 RW shift_pttn_data[49:40]. Default 0. */
106 /* Bit 19:10 RW shift_pttn_data[ 9: 0]. Default 0. */
107 /* Bit  9: 0 RW shift_pttn_data[19:10]. Default 0. */
110 /* Bit 25:16 RW tmds_clk_pttn[19:10]. Default 0. */
111 /* Bit  9: 0 RW tmds_clk_pttn[ 9: 0]. Default 0. */
114 /* Bit 25:16 RW tmds_clk_pttn[39:30]. Default 0. */
115 /* Bit  9: 0 RW tmds_clk_pttn[29:20]. Default 0. */
119  * used when TMDS CLK rate = TMDS character rate /4. Default 0.
120  * Bit 0 R  Reserved. Default 0.
127  * failure, write 1 to clear the failure flag.  Default 0.