43 	struct dw_hdmi hdmi;  member
61 static unsigned int dw_hdmi_top_read(struct dw_hdmi *hdmi, unsigned int addr)  in dw_hdmi_top_read()  argument
66 	writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);  in dw_hdmi_top_read()
67 	writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);  in dw_hdmi_top_read()
70 	data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG);  in dw_hdmi_top_read()
71 	data = readl(hdmi->ioaddr + HDMITX_TOP_DATA_REG);  in dw_hdmi_top_read()
76 static inline void dw_hdmi_top_write(struct dw_hdmi *hdmi,  in dw_hdmi_top_write()  argument
80 	writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);  in dw_hdmi_top_write()
81 	writel(addr & 0xffff, hdmi->ioaddr + HDMITX_TOP_ADDR_REG);  in dw_hdmi_top_write()
84 	writel(data, hdmi->ioaddr + HDMITX_TOP_DATA_REG);  in dw_hdmi_top_write()
87 static inline void dw_hdmi_top_write_bits(struct dw_hdmi *hdmi,  in dw_hdmi_top_write_bits()  argument
92 	unsigned int data = dw_hdmi_top_read(hdmi, addr);  in dw_hdmi_top_write_bits()
96 	dw_hdmi_top_write(hdmi, addr, data);  in dw_hdmi_top_write_bits()
99 static u8 dw_hdmi_dwc_read(struct dw_hdmi *hdmi, int addr)  in dw_hdmi_dwc_read()  argument
104 	writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);  in dw_hdmi_dwc_read()
105 	writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);  in dw_hdmi_dwc_read()
108 	data = readl(hdmi->ioaddr + HDMITX_DWC_DATA_REG);  in dw_hdmi_dwc_read()
109 	data = readl(hdmi->ioaddr + HDMITX_DWC_DATA_REG);  in dw_hdmi_dwc_read()
114 static inline void dw_hdmi_dwc_write(struct dw_hdmi *hdmi, u8 data, int addr)  in dw_hdmi_dwc_write()  argument
117 	writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);  in dw_hdmi_dwc_write()
118 	writel(addr & 0xffff, hdmi->ioaddr + HDMITX_DWC_ADDR_REG);  in dw_hdmi_dwc_write()
121 	writel(data, hdmi->ioaddr + HDMITX_DWC_DATA_REG);  in dw_hdmi_dwc_write()
124 static inline void dw_hdmi_dwc_write_bits(struct dw_hdmi *hdmi,  in dw_hdmi_dwc_write_bits()  argument
129 	u8 data = dw_hdmi_dwc_read(hdmi, addr);  in dw_hdmi_dwc_write_bits()
134 	dw_hdmi_dwc_write(hdmi, data, addr);  in dw_hdmi_dwc_write_bits()
167 	ret = dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);  in meson_dw_hdmi_read_edid()
257 static int meson_dw_hdmi_phy_init(struct dw_hdmi *hdmi, uint pixel_clock)  in meson_dw_hdmi_phy_init()  argument
259 	struct meson_dw_hdmi *priv = container_of(hdmi, struct meson_dw_hdmi,  in meson_dw_hdmi_phy_init()
260 						  hdmi);  in meson_dw_hdmi_phy_init()
268 	dw_hdmi_top_write(hdmi, HDMITX_TOP_SW_RESET,  0);  in meson_dw_hdmi_phy_init()
271 	dw_hdmi_top_write_bits(hdmi, HDMITX_TOP_CLK_CNTL, 0x3, 0x3);  in meson_dw_hdmi_phy_init()
272 	dw_hdmi_top_write_bits(hdmi, HDMITX_TOP_CLK_CNTL, 0x3 << 4, 0x3 << 4);  in meson_dw_hdmi_phy_init()
275 	dw_hdmi_top_write(hdmi, HDMITX_TOP_BIST_CNTL, BIT(12));  in meson_dw_hdmi_phy_init()
278 	dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f);  in meson_dw_hdmi_phy_init()
279 	dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f);  in meson_dw_hdmi_phy_init()
282 	dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1);  in meson_dw_hdmi_phy_init()
284 	dw_hdmi_top_write(hdmi, HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2);  in meson_dw_hdmi_phy_init()
320 	return dw_hdmi_enable(&priv->hdmi, edid);  in meson_dw_hdmi_enable()
323 static int meson_dw_hdmi_wait_hpd(struct dw_hdmi *hdmi)  in meson_dw_hdmi_wait_hpd()  argument
329 		if (dw_hdmi_top_read(hdmi, HDMITX_TOP_STAT0))  in meson_dw_hdmi_wait_hpd()
348 	priv->hdmi.ioaddr = (ulong)dev_remap_addr_index(dev, 0);  in meson_dw_hdmi_probe()
349 	if (!priv->hdmi.ioaddr)  in meson_dw_hdmi_probe()
356 	priv->hdmi.hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24;  in meson_dw_hdmi_probe()
357 	priv->hdmi.hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_YUV8_1X24;  in meson_dw_hdmi_probe()
358 	priv->hdmi.phy_set = meson_dw_hdmi_phy_init;  in meson_dw_hdmi_probe()
359 	priv->hdmi.write_reg = dw_hdmi_dwc_write;  in meson_dw_hdmi_probe()
360 	priv->hdmi.read_reg = dw_hdmi_dwc_read;  in meson_dw_hdmi_probe()
361 	priv->hdmi.i2c_clk_high = 0x67;  in meson_dw_hdmi_probe()
362 	priv->hdmi.i2c_clk_low = 0x78;  in meson_dw_hdmi_probe()
364 	ret = device_get_supply_regulator(dev, "hdmi-supply", &supply);  in meson_dw_hdmi_probe()
404 	writel_bits(BIT(15), BIT(15), priv->hdmi.ioaddr + HDMITX_TOP_CTRL_REG);  in meson_dw_hdmi_probe()
405 	writel_bits(BIT(15), BIT(15), priv->hdmi.ioaddr + HDMITX_DWC_CTRL_REG);  in meson_dw_hdmi_probe()
408 	dw_hdmi_top_write(&priv->hdmi, HDMITX_TOP_SW_RESET,  0);  in meson_dw_hdmi_probe()
410 	dw_hdmi_top_write(&priv->hdmi, HDMITX_TOP_CLK_CNTL, 0xff);  in meson_dw_hdmi_probe()
412 	dw_hdmi_init(&priv->hdmi);  in meson_dw_hdmi_probe()
413 	dw_hdmi_phy_init(&priv->hdmi);  in meson_dw_hdmi_probe()
416 	ret = meson_dw_hdmi_wait_hpd(&priv->hdmi);  in meson_dw_hdmi_probe()
418 		debug("hdmi can not get hpd signal\n");  in meson_dw_hdmi_probe()
429 	{ .compatible = "amlogic,meson-gxbb-dw-hdmi",
431 	{ .compatible = "amlogic,meson-gxl-dw-hdmi",
433 	{ .compatible = "amlogic,meson-gxm-dw-hdmi",