1 // SPDX-License-Identifier: GPL-2.0+
3  * (C) Copyright 2016-2018 ARM Ltd.
127 	while (tries--) {  in malidp_wait_configdone()
128 		status = readl(malidp->dc_status_addr);  in malidp_wait_configdone()
129 		if ((status >> malidp->config_bit_shift) & 1)  in malidp_wait_configdone()
135 		return -ETIMEDOUT;  in malidp_wait_configdone()
145 	setbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift);  in malidp_enter_config()
154 	clrbits_le32(malidp->dc_control_addr, 1 << malidp->config_bit_shift);  in malidp_leave_config()
161 	u32 val = MALIDP_H_SYNCWIDTH(timings->hsync_len.typ) |  in malidp_setup_timings()
162 		  MALIDP_V_SYNCWIDTH(timings->vsync_len.typ);  in malidp_setup_timings()
163 	writel(val, malidp->base_addr + malidp->modeset_regs_offset +  in malidp_setup_timings()
165 	val = MALIDP_H_BACKPORCH(timings->hback_porch.typ) |  in malidp_setup_timings()
166 		MALIDP_H_FRONTPORCH(timings->hfront_porch.typ);  in malidp_setup_timings()
167 	writel(val, malidp->base_addr + malidp->modeset_regs_offset +  in malidp_setup_timings()
169 	val = MALIDP_V_BACKPORCH(timings->vback_porch.typ) |  in malidp_setup_timings()
170 		MALIDP_V_FRONTPORCH(timings->vfront_porch.typ);  in malidp_setup_timings()
171 	writel(val, malidp->base_addr + malidp->modeset_regs_offset +  in malidp_setup_timings()
173 	val = MALIDP_H_ACTIVE(timings->hactive.typ) |  in malidp_setup_timings()
174 		MALIDP_V_ACTIVE(timings->vactive.typ);  in malidp_setup_timings()
175 	writel(val, malidp->base_addr + malidp->modeset_regs_offset +  in malidp_setup_timings()
177 	/* default output bit-depth per colour is 8 bits */  in malidp_setup_timings()
178 	writel(0x080808, malidp->base_addr + malidp->modeset_regs_offset +  in malidp_setup_timings()
187 	if (clk_set_rate(&malidp->pxlclk, timings->pixelclock.typ) == 0)  in malidp_setup_mode()
188 		return -EIO;  in malidp_setup_mode()
192 	err = display_enable(malidp->display, 8, timings);  in malidp_setup_mode()
206 	writel(MALIDP_FORMAT_ARGB8888, malidp->base_addr + layer_offset +  in malidp_setup_layer()
209 	val = MALIDP_CMP_V_SIZE(timings->vactive.typ) |  in malidp_setup_layer()
210 		MALIDP_CMP_H_SIZE(timings->hactive.typ);  in malidp_setup_layer()
211 	writel(val, malidp->base_addr + layer_offset +  in malidp_setup_layer()
214 	val = MALIDP_IN_V_SIZE(timings->vactive.typ) |  in malidp_setup_layer()
215 		MALIDP_IN_H_SIZE(timings->hactive.typ);  in malidp_setup_layer()
216 	writel(val, malidp->base_addr + layer_offset + MALIDP_LAYER_IN_SIZE);  in malidp_setup_layer()
218 	writel(timings->hactive.typ << 2, malidp->base_addr + layer_offset +  in malidp_setup_layer()
221 	writel(lower_32_bits(fb_addr), malidp->base_addr + layer_offset +  in malidp_setup_layer()
223 	writel(upper_32_bits(fb_addr), malidp->base_addr + layer_offset +  in malidp_setup_layer()
226 	setbits_le32(malidp->base_addr + layer_offset +  in malidp_setup_layer()
232 	setbits_le32(malidp->cval_addr, 1);  in malidp_set_configvalid()
247 	priv->display = disp_dev;  in malidp_update_timings_from_edid()
270 		return -EINVAL;  in malidp_probe()
272 	err = clk_get_by_name(dev, "pxlclk", &priv->pxlclk);  in malidp_probe()
277 	err = clk_get_by_name(dev, "aclk", &priv->aclk);  in malidp_probe()
297 		uc_plat->base = fb_base;  in malidp_probe()
298 		uc_plat->size = fb_size;  in malidp_probe()
306 	uc_priv->xsize = (ushort)value;  in malidp_probe()
311 	uc_priv->ysize = (ushort)value;  in malidp_probe()
315 		err = -EINVAL;  in malidp_probe()
318 		uc_priv->bpix = VIDEO_BPP32;  in malidp_probe()
321 	uc_priv->rot = 0;  in malidp_probe()
322 	priv->base_addr = (phys_addr_t)dev_read_addr(dev);  in malidp_probe()
324 	clk_enable(&priv->pxlclk);  in malidp_probe()
325 	clk_enable(&priv->aclk);  in malidp_probe()
327 	value = malidp_get_hwid(priv->base_addr);  in malidp_probe()
328 	printf("Display: Arm Mali DP%3x r%dp%d\n", MALIDP_PRODUCT_ID(value),  in malidp_probe()
333 		priv->modeset_regs_offset = 0x28;  in malidp_probe()
334 		priv->dc_status_addr = priv->base_addr;  in malidp_probe()
335 		priv->dc_control_addr = priv->base_addr + 0xc;  in malidp_probe()
336 		priv->cval_addr = priv->base_addr + 0xf00;  in malidp_probe()
337 		priv->config_bit_shift = 17;  in malidp_probe()
338 		priv->clear_irq = 0;  in malidp_probe()
340 		priv->modeset_regs_offset = 0x30;  in malidp_probe()
341 		priv->dc_status_addr = priv->base_addr + MALIDP_DC_STATUS;  in malidp_probe()
342 		priv->dc_control_addr = priv->base_addr + MALIDP_DC_CONTROL;  in malidp_probe()
343 		priv->cval_addr = priv->base_addr + MALIDP_DC_CFG_VALID;  in malidp_probe()
344 		priv->config_bit_shift = 16;  in malidp_probe()
345 		priv->clear_irq = MALIDP_REG_CLEARIRQ;  in malidp_probe()
354 	writel(0, priv->dc_status_addr + MALIDP_REG_MASKIRQ);  in malidp_probe()
355 	writel(0xffffffff, priv->dc_status_addr + priv->clear_irq);  in malidp_probe()
362 			   (phys_addr_t)uc_plat->base);  in malidp_probe()
373 	clk_free(&priv->aclk);  in malidp_probe()
375 	clk_free(&priv->pxlclk);  in malidp_probe()
385 	uc_plat->size = 4 * 2048 * 2048;  in malidp_bind()
391 	{ .compatible = "arm,mali-dp500" },
392 	{ .compatible = "arm,mali-dp550" },
393 	{ .compatible = "arm,mali-dp650" },